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mtd: spi-nor-core: Parse xSPI Profile 1.0 table
This table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command. The default dummy cycles for a fast octal DTR read are set to 20. Since there is no simple way of determining the dummy cycles needed for the fast read command, flashes that use a different value should update it in their flash-specific hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pratyush Yadav
Jagan Teki
parent
9ec5ea0127
commit
4d40e82663
2 changed files with 107 additions and 0 deletions
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@ -21,6 +21,7 @@
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#include <linux/log2.h>
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#include <linux/math64.h>
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#include <linux/sizes.h>
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#include <linux/bitfield.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/spi-nor.h>
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@ -40,6 +41,8 @@
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#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
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#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
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struct sfdp_parameter_header {
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u8 id_lsb;
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u8 minor;
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@ -58,6 +61,7 @@ struct sfdp_parameter_header {
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#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
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#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
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#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
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#define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
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#define SFDP_SIGNATURE 0x50444653U
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#define SFDP_JESD216_MAJOR 1
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@ -155,6 +159,16 @@ struct sfdp_header {
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#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
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#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
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/* xSPI Profile 1.0 table (from JESD216D.01). */
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#define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
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#define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
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#define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
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#define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
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#define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
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#define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
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#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
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#define PROFILE1_DUMMY_DEFAULT 20
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struct sfdp_bfpt {
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u32 dwords[BFPT_DWORD_MAX];
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};
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@ -2095,6 +2109,86 @@ spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
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return ret;
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}
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/**
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* spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
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* @nor: pointer to a 'struct spi_nor'
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* @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
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* the 4-Byte Address Instruction Table length and version.
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* @params: pointer to the 'struct spi_nor_flash_parameter' to be.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_parse_profile1(struct spi_nor *nor,
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const struct sfdp_parameter_header *profile1_header,
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struct spi_nor_flash_parameter *params)
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{
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u32 *table, opcode, addr;
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size_t len;
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int ret, i;
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u8 dummy;
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len = profile1_header->length * sizeof(*table);
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table = kmalloc(len, GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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addr = SFDP_PARAM_HEADER_PTP(profile1_header);
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ret = spi_nor_read_sfdp(nor, addr, len, table);
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if (ret)
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goto out;
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/* Fix endianness of the table DWORDs. */
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for (i = 0; i < profile1_header->length; i++)
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table[i] = le32_to_cpu(table[i]);
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/* Get 8D-8D-8D fast read opcode and dummy cycles. */
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opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
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/*
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* We don't know what speed the controller is running at. Find the
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* dummy cycles for the fastest frequency the flash can run at to be
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* sure we are never short of dummy cycles. A value of 0 means the
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* frequency is not supported.
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*
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* Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
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* flashes set the correct value if needed in their fixup hooks.
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*/
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dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
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if (!dummy)
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dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
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if (!dummy)
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dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
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if (!dummy)
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dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
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if (!dummy)
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dummy = PROFILE1_DUMMY_DEFAULT;
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/* Round up to an even value to avoid tripping controllers up. */
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dummy = ROUND_UP_TO(dummy, 2);
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/* Update the fast read settings. */
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spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
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0, dummy, opcode,
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SNOR_PROTO_8_8_8_DTR);
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/*
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* Set the Read Status Register dummy cycles and dummy address bytes.
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*/
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if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
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params->rdsr_dummy = 8;
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else
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params->rdsr_dummy = 4;
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if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
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params->rdsr_addr_nbytes = 4;
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else
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params->rdsr_addr_nbytes = 0;
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out:
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kfree(table);
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return ret;
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}
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/**
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* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
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* @nor: pointer to a 'struct spi_nor'
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@ -2197,6 +2291,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
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err = spi_nor_parse_microchip_sfdp(nor, param_header);
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break;
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case SFDP_PROFILE1_ID:
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err = spi_nor_parse_profile1(nor, param_header, params);
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break;
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default:
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break;
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}
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@ -2926,6 +3024,8 @@ int spi_nor_scan(struct spi_nor *nor)
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if (ret)
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return ret;
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nor->rdsr_dummy = params.rdsr_dummy;
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nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
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nor->name = mtd->name;
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nor->size = mtd->size;
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nor->erase_size = mtd->erasesize;
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@ -391,6 +391,8 @@ enum spi_nor_pp_command_index {
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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u8 rdsr_dummy;
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u8 rdsr_addr_nbytes;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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@ -445,6 +447,9 @@ struct spi_flash {
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* @read_opcode: the read opcode
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* @read_dummy: the dummy needed by the read operation
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* @program_opcode: the program opcode
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* @rdsr_dummy dummy cycles needed for Read Status Register command.
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* @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
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* command.
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* @bank_read_cmd: Bank read cmd
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* @bank_write_cmd: Bank write cmd
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* @bank_curr: Current flash bank
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@ -486,6 +491,8 @@ struct spi_nor {
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u8 read_opcode;
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u8 read_dummy;
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u8 program_opcode;
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u8 rdsr_dummy;
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u8 rdsr_addr_nbytes;
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 bank_read_cmd;
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u8 bank_write_cmd;
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