mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
* Patch by Tolunay Orkun, 5 Mar 2004:
Fix early board initialization for Cogent CSB272 board * Patch by Ed Okerson, 3 Mar 2004: fix CFI flash writes for little endian systems * Patch by Reinhard Meyer, 01 Mar 2004: generalize USB and IDE support for MPC5200 with according changes to IceCube.h and TOP5200.h add Am29LV256 256 MBit FLASH support for TOP5200 boards add info about USB and IDE to README
This commit is contained in:
wdenk
parent
c3f9d4939a
commit
4d13cbad1c
13 changed files with 249 additions and 41 deletions
12
CHANGELOG
12
CHANGELOG
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@ -2,6 +2,18 @@
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Changes for U-Boot 1.0.2:
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======================================================================
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* Patch by Tolunay Orkun, 5 Mar 2004:
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Fix early board initialization for Cogent CSB272 board
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* Patch by Ed Okerson, 3 Mar 2004:
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fix CFI flash writes for little endian systems
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* Patch by Reinhard Meyer, 01 Mar 2004:
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generalize USB and IDE support for MPC5200 with according
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changes to IceCube.h and TOP5200.h
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add Am29LV256 256 MBit FLASH support for TOP5200 boards
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add info about USB and IDE to README
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* Patch by Yuli Barcohen, 4 Mar 2004:
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Fix problems with GCC 3.3.x which changed handling of global
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variables explicitly initialized to zero (now in .bss instead of
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18
README
18
README
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@ -660,10 +660,13 @@ The following options need to be configured:
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one partition type as well.
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- IDE Reset method:
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CONFIG_IDE_RESET_ROUTINE
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CONFIG_IDE_RESET_ROUTINE - this is defined in several
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board configurations files but used nowhere!
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Set this to define that instead of a reset Pin, the
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routine ide_set_reset(int idereset) will be used.
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CONFIG_IDE_RESET - is this is defined, IDE Reset will
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be performed by calling the function
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ide_set_reset(int reset)
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which has to be defined in a board specific file
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- ATAPI Support:
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CONFIG_ATAPI
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@ -728,7 +731,7 @@ The following options need to be configured:
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- USB Support:
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At the moment only the UHCI host controller is
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supported (PIP405, MIP405); define
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supported (PIP405, MIP405, MPC5200); define
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CONFIG_USB_UHCI to enable it.
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define CONFIG_USB_KEYBOARD to enable the USB Keyboard
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end define CONFIG_USB_STORAGE to enable the USB
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@ -736,6 +739,13 @@ The following options need to be configured:
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Note:
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Supported are USB Keyboards and USB Floppy drives
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(TEAC FD-05PUB).
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MPC5200 USB requires additional defines:
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CONFIG_USB_CLOCK
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for 528 MHz Clock: 0x0001bbbb
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CONFIG_USB_CONFIG
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for differential drivers: 0x00001000
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for single ended drivers: 0x00005000
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- MMC Support:
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The MMC controller on the Intel PXA is supported. To
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@ -21,9 +21,8 @@
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* MA 02111-1307 USA
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*/
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#include <asm/u-boot.h>
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#include <asm/processor.h>
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <405gp_enet.h>
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@ -57,10 +56,10 @@ int pll_init(void)
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}
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/*
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* board_pre_init: do any preliminary board initialization
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* board_early_init_f: do early board initialization
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*
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*/
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int board_pre_init(void)
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int board_early_init_f(void)
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{
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/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
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(void) get_clocks();
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@ -172,3 +171,4 @@ int last_stage_init(void)
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return 0; /* success */
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}
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@ -40,9 +40,11 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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#define FLASH_CYCLE2 0x02aa
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#define FLASH_ID1 0
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#define FLASH_ID2 1
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#define FLASH_ID3 0x0e
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#define FLASH_ID4 0x0F
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#endif
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#if defined (CONFIG_TOP5200)
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#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFF
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@ -54,6 +56,24 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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#define FLASH_CYCLE2 0x0555
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#define FLASH_ID1 0
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#define FLASH_ID2 2
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#define FLASH_ID3 0x1c
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#define FLASH_ID4 0x1E
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#endif
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#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFF
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x02aa
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#define FLASH_ID1 0
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#define FLASH_ID2 1
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#define FLASH_ID3 0x0E
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#define FLASH_ID4 0x0F
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#endif
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/*-----------------------------------------------------------------------
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@ -183,6 +203,15 @@ void flash_print_info (flash_info_t *info)
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case FLASH_AM160B:
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fmt = "29LV160%s (16 Mbit, %s)\n";
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break;
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case FLASH_AMLV640U:
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fmt = "29LV640M (64 Mbit)\n";
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break;
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case FLASH_AMDLV065D:
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fmt = "29LV065D (64 Mbit)\n";
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break;
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case FLASH_AMLV256U:
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fmt = "29LV256M (256 Mbit)\n";
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break;
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default:
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fmt = "Unknown Chip Type\n";
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break;
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@ -239,7 +268,6 @@ void flash_print_info (flash_info_t *info)
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ulong flash_get_size (FPWV *addr, flash_info_t *info)
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{
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int i;
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ulong offset;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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@ -278,27 +306,64 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00200000;
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#ifdef CFG_LOWBOOT
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offset = 0;
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#else
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offset = 0x00e00000;
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#endif
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info->start[0] = (ulong)addr + offset;
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info->start[1] = (ulong)addr + offset + 0x4000;
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info->start[2] = (ulong)addr + offset + 0x6000;
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info->start[3] = (ulong)addr + offset + 0x8000;
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info->start[0] = (ulong)addr;
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info->start[1] = (ulong)addr + 0x4000;
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info->start[2] = (ulong)addr + 0x6000;
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info->start[3] = (ulong)addr + 0x8000;
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for (i = 4; i < info->sector_count; i++)
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{
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info->start[i] = (ulong)addr + offset + 0x10000 * (i-3);
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info->start[i] = (ulong)addr + 0x10000 * (i-3);
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}
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break;
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case (FPW)AMD_ID_LV065D:
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info->flash_id += FLASH_AMDLV065D;
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info->sector_count = 128;
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info->size = 0x00800000;
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for (i = 0; i < info->sector_count; i++)
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{
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info->start[i] = (ulong)addr + 0x10000 * i;
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}
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break;
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case (FPW)AMD_ID_MIRROR:
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/* MIRROR BIT FLASH, read more ID bytes */
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if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
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(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
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{
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info->flash_id += FLASH_AMLV640U;
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info->sector_count = 128;
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info->size = 0x00800000;
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for (i = 0; i < info->sector_count; i++)
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{
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info->start[i] = (ulong)addr + 0x10000 * i;
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}
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break;
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}
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if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
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(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
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{
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/* attention: only the first 16 MB will be used in u-boot */
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info->flash_id += FLASH_AMLV256U;
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info->sector_count = 256;
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info->size = 0x01000000;
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for (i = 0; i < info->sector_count; i++)
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{
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info->start[i] = (ulong)addr + 0x10000 * i;
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}
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break;
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}
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/* fall thru to here ! */
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default:
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printf ("unknown AMD device=%x ", (FPW)addr[FLASH_ID2]);
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printf ("unknown AMD device=%x %x %x",
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(FPW)addr[FLASH_ID2],
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(FPW)addr[FLASH_ID3],
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(FPW)addr[FLASH_ID4]);
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* => no or unknown flash */
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info->size = 0x800000;
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break;
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}
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/* Put FLASH back in read mode */
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@ -329,6 +394,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM160B:
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case FLASH_AMLV640U:
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break;
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case FLASH_UNKNOWN:
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default:
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@ -113,11 +113,15 @@ int checkboard (void)
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#if defined (CONFIG_EVAL5200)
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puts ("Board: EMK TOP5200 on EVAL5200\n");
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#else
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#if defined (CONFIG_LITE5200)
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puts ("Board: LITE5200\n");
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#else
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#if defined (CONFIG_MINI5200)
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puts ("Board: EMK TOP5200 on MINI5200\n");
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#else
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puts ("Board: EMK TOP5200\n");
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#endif
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#endif
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#endif
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return 0;
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}
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@ -155,10 +159,11 @@ void flash_afterinit(uint bank, ulong start, ulong size)
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*****************************************************************************/
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int misc_init_r (void)
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{
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#if !defined (CONFIG_LITE5200)
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/* read 'factory' part of EEPROM */
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extern void read_factory_r (void);
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read_factory_r ();
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#endif
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return (0);
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}
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@ -175,3 +180,23 @@ void pci_init_board(void)
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pci_mpc5xxx_init(&hose);
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}
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#endif
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/*****************************************************************************
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* provide the PCI Reset Function
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*****************************************************************************/
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#ifdef CFG_CMD_IDE
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#define GPIO_PSC1_4 0x01000000ul
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void ide_set_reset (int idereset)
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{
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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}
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/* Configure PSC1_4 as GPIO output for ATA reset */
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/* (it does not matter we do this every time) */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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}
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#endif
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@ -210,25 +210,25 @@ void pci_init_board(void)
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#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
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#define GPIO_PSC1_4 0x01000000ul
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#define GPIO_PSC1_4 0x01000000UL
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void init_ide_reset (void)
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{
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printf ("init_ide_reset\n");
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debug ("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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}
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void ide_set_reset (int idereset)
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{
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printf ("ide_reset(%d)\n", idereset);
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debug ("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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}
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}
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#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
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@ -503,6 +503,7 @@ void ide_init (void)
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#endif /* CONFIG_IDE_8xx_PCCARD */
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#ifdef CONFIG_IDE_PREINIT
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extern int ide_preinit (void);
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WATCHDOG_RESET();
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if (ide_preinit ()) {
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@ -1532,12 +1532,13 @@ int usb_lowlevel_init(void)
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{
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/* Set the USB Clock */
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*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CDMFDC5xxx;
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*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
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/* remove all USB bits first before ORing in ours */
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
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/* Activate USB port */
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_GPSCFG5xxx;
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
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memset (&gohci, 0, sizeof (ohci_t));
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memset (&urb_priv, 0, sizeof (urb_priv_t));
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|
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@ -724,18 +724,42 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
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*/
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static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
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{
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#if defined(__LITTLE_ENDIAN)
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unsigned short w;
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unsigned int l;
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unsigned long long ll;
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#endif
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switch (info->portwidth) {
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case FLASH_CFI_8BIT:
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cword->c = c;
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break;
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case FLASH_CFI_16BIT:
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#if defined(__LITTLE_ENDIAN)
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w = c;
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w <<= 8;
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cword->w = (cword->w >> 8) | w;
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#else
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cword->w = (cword->w << 8) | c;
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#endif
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break;
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case FLASH_CFI_32BIT:
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#if defined(__LITTLE_ENDIAN)
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l = c;
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l <<= 24;
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cword->l = (cword->l >> 8) | l;
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#else
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cword->l = (cword->l << 8) | c;
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#endif
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break;
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case FLASH_CFI_64BIT:
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#if defined(__LITTLE_ENDIAN)
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ll = c;
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ll <<= 56;
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cword->ll = (cword->ll >> 8) | ll;
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#else
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cword->ll = (cword->ll << 8) | c;
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#endif
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break;
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}
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}
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|
|
|
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@ -305,8 +305,8 @@
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CDMFDC5xxx 0x0001BBBB
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#define CONFIG_USB_GPSCFG5xxx 0x00001000
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
|
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|
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
|
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|
|
|
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|
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@ -63,7 +63,7 @@
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
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|
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|
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#ifdef CONFIG_EVAL5200 /* PCI is supported with Evaluation board only */
|
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#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
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/*
|
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* PCI Mapping:
|
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* 0x40000000 - 0x4fffffff - PCI Memory
|
||||
|
|
@ -89,11 +89,41 @@
|
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|
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#endif
|
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|
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/* USB */
|
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#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
|
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|
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# define CONFIG_USB_OHCI
|
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# define CONFIG_USB_CLOCK 0x0001bbbb
|
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# define CONFIG_USB_CONFIG 0x00005000
|
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# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
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# define CONFIG_DOS_PARTITION
|
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# define CONFIG_USB_STORAGE
|
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|
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#else
|
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|
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# define ADD_USB_CMD 0
|
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|
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#endif
|
||||
|
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/* IDE */
|
||||
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
|
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|
||||
# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
|
||||
# define CONFIG_DOS_PARTITION
|
||||
|
||||
#else
|
||||
|
||||
# define ADD_IDE_CMD 0
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
ADD_PCI_CMD | \
|
||||
ADD_USB_CMD | \
|
||||
ADD_IDE_CMD | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
|
|
@ -110,11 +140,13 @@
|
|||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* low boot
|
||||
* MUST be low boot - HIGHBOOT is not supported anymore
|
||||
*/
|
||||
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
|
||||
# define CFG_LOWBOOT 1
|
||||
# define CFG_LOWBOOT16 1
|
||||
#else
|
||||
# error "TEXT_BASE must be 0xff000000"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -168,7 +200,7 @@
|
|||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
|
||||
|
||||
#if defined (CONFIG_SOFT_I2C)
|
||||
# define SDA0 0x40
|
||||
|
|
@ -187,12 +219,16 @@
|
|||
# define I2C_TRISTATE {DDR0&=~SDA0;}
|
||||
# define CFG_I2C_SPEED 100000
|
||||
# define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_EEPROM_ADDR 0x57
|
||||
#define CFG_I2C_FACT_ADDR 0x57
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_HARD_I2C)
|
||||
# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
# define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
# define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_EEPROM_ADDR 0x54
|
||||
#define CFG_I2C_FACT_ADDR 0x54
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -242,14 +278,12 @@
|
|||
#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
|
||||
#define CFG_ENV_OFFSET 0x1000
|
||||
#define CFG_ENV_SIZE 0x0700
|
||||
#define CFG_I2C_EEPROM_ADDR 0x57
|
||||
|
||||
/*
|
||||
* VPD settings
|
||||
*/
|
||||
#define CFG_FACT_OFFSET 0x1800
|
||||
#define CFG_FACT_SIZE 0x0800
|
||||
#define CFG_I2C_FACT_ADDR 0x57
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
|
|
@ -310,7 +344,7 @@
|
|||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_LOAD_ADDR 0x200000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
|
|
@ -345,4 +379,36 @@
|
|||
|
||||
#define CFG_RESET_ADDRESS 0x7f000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
|
||||
#define CONFIG_IDE_RESET 1
|
||||
#define CONFIG_IDE_PREINIT
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (0x0060)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET (0x005c)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CFG_ATA_STRIDE 4
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
|
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
|
||||
#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init() */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
|
||||
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
|
|
|
|||
|
|
@ -183,6 +183,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_LV640U_3 0x22012201 /* 3d ID word for AM29LV640M at 0x3c */
|
||||
#define AMD_ID_LV128U_2 0x22122212 /* 2d ID word for AM29LV128M at 0x38 */
|
||||
#define AMD_ID_LV128U_3 0x22002200 /* 3d ID word for AM29LV128M at 0x3c */
|
||||
#define AMD_ID_LV256U_2 0x22122212 /* 2d ID word for AM29LV256M at 0x38 */
|
||||
#define AMD_ID_LV256U_3 0x22012201 /* 3d ID word for AM29LV256M at 0x3c */
|
||||
|
||||
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
|
||||
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
|
||||
|
|
@ -345,6 +347,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
|
||||
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
|
||||
/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
|
||||
#define FLASH_28F256L18T 0x00B0
|
||||
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
|
||||
|
|
|
|||
Loading…
Reference in a new issue