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net: altera_tse: use BIT macro
Replace numerical bit shift with BIT macro in altera_tse :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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1 changed files with 15 additions and 15 deletions
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@ -14,11 +14,11 @@
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#define __packed_1_ __packed __aligned(1)
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/* SGDMA Stuff */
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#define ALT_SGDMA_STATUS_BUSY_MSK 0x00000010
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#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
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#define ALT_SGDMA_CONTROL_RUN_MSK 0x00000020
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK 0x00000040
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK 0x00010000
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#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
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/*
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* Descriptor control bit masks & offsets
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@ -27,10 +27,10 @@
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* The following bit-offsets are expressed relative to the LSB of
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* the control register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK 0x00000001
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK 0x00000002
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK 0x00000004
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK 0x00000080
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
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/*
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* Descriptor status bit masks & offsets
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@ -39,7 +39,7 @@
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* The following bit-offsets are expressed relative to the LSB of
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* the status register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK 0x00000080
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#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
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/*
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* The SGDMA controller buffer descriptor allocates
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@ -85,12 +85,12 @@ struct alt_sgdma_registers {
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};
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/* TSE Stuff */
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#define ALTERA_TSE_CMD_TX_ENA_MSK 0x00000001
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#define ALTERA_TSE_CMD_RX_ENA_MSK 0x00000002
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#define ALTERA_TSE_CMD_ETH_SPEED_MSK 0x00000008
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#define ALTERA_TSE_CMD_HD_ENA_MSK 0x00000400
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#define ALTERA_TSE_CMD_SW_RESET_MSK 0x00002000
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#define ALTERA_TSE_CMD_ENA_10_MSK 0x02000000
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#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
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#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
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#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
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#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
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#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
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#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
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#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
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