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https://github.com/AsahiLinux/u-boot
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Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-marvell into next
- mvebu: kwboot: Fix UART booting (Pali) - mvebu: doc: Misc updates / fixes (Pali) - kirkwood: Early init enhancements, e.g. for DEBUG UART (Pali & Tony) - mvebu: Enable NAND flash for Thecus N2350 board (Tony) - mvebu: Set common SPI flash default speed and mode (Tony)
This commit is contained in:
commit
4b635046b5
12 changed files with 84 additions and 70 deletions
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@ -5,9 +5,11 @@ config FEROCEON_88FR131
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config KW88F6192
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bool
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select ARCH_VERY_EARLY_INIT
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config KW88F6281
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bool
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select ARCH_VERY_EARLY_INIT
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config SHEEVA_88SV131
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bool
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@ -6,6 +6,7 @@
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obj-y = cpu.o
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obj-y += cache.o
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obj-y += lowlevel.o
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obj-y += mpp.o
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# cpu.o and cache.o contain CP15 instructions which cannot be run in
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@ -189,9 +189,6 @@ int arch_cpu_init(void)
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struct kwcpu_registers *cpureg =
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(struct kwcpu_registers *)KW_CPU_REG_BASE;
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
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/* Enable and invalidate L2 cache in write through mode */
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writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
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invalidate_l2_cache();
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12
arch/arm/mach-kirkwood/lowlevel.S
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12
arch/arm/mach-kirkwood/lowlevel.S
Normal file
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#include <config.h>
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#include <linux/linkage.h>
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ENTRY(arch_very_early_init)
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/* Move internal registers from KW_OFFSET_REG to KW_REGS_PHY_BASE */
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ldr r0, =KW_REGS_PHY_BASE
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ldr r1, =KW_OFFSET_REG
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str r0, [r1]
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bx lr
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ENDPROC(arch_very_early_init)
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@ -423,6 +423,16 @@ config SECURED_MODE_CSK_INDEX
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default 0
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depends on SECURED_MODE_IMAGE
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config SF_DEFAULT_SPEED
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int "Default speed for SPI flash in Hz"
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default 10000000
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depends on MVEBU_SPL_BOOT_DEVICE_SPI
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config SF_DEFAULT_MODE
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hex "Default mode for SPI flash"
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default 0x0
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depends on MVEBU_SPL_BOOT_DEVICE_SPI
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source "board/solidrun/clearfog/Kconfig"
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source "board/kobol/helios4/Kconfig"
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@ -69,6 +69,9 @@ CONFIG_SYS_64BIT_LBA=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_PXA3XX=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_SPEED=50000000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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@ -15,8 +15,11 @@ CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0xE0000
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CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
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CONFIG_SYS_PROMPT="NSA310s> "
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CONFIG_DEBUG_UART_BASE=0xf1012000
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CONFIG_DEBUG_UART_CLOCK=166666667
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CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
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CONFIG_SYS_LOAD_ADDR=0x800000
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CONFIG_DEBUG_UART=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_PREBOOT=y
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@ -50,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_PHY_MARVELL=y
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CONFIG_MVGBE=y
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CONFIG_MII=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_UBIFS_SILENCE_MSG=y
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@ -69,7 +69,7 @@ To get a BootROM help, type this command followed by ENTER key:
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.IP
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Armada 38x BootROM has a bug which cause that BootROM's standard output
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is turned off on UART when SPI-NOR contains valid boot image. Nevertheless
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is turned off on UART when default boot source location contains valid boot image. Nevertheless
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BootROM's standard input and BootROM's terminal echo are active and working
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fine. To workaround this BootROM bug with standard output, it is possible
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to manually overwrite BootROM variables stored in SRAM which BootROM use
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@ -9,7 +9,6 @@
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#include "ddr_ml_wrapper.h"
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#include "mv_ddr_plat.h"
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#include "seq_exec.h"
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#include "ddr3_logging_def.h"
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#include "ddr3_training_hw_algo.h"
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#include "ddr3_training_ip.h"
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@ -1,64 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _SEQ_EXEC_H
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#define _SEQ_EXEC_H
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#define NA 0xff
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#define DEFAULT_PARAM 0
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#define MV_BOARD_TCLK_ERROR 0xffffffff
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#define NO_DATA 0xffffffff
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#define MAX_DATA_ARRAY 5
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#define FIRST_CELL 0
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/* Operation types */
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enum mv_op {
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WRITE_OP,
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DELAY_OP,
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POLL_OP,
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};
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/* Operation parameters */
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struct op_params {
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u32 unit_base_reg;
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u32 unit_offset;
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u32 mask;
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u32 data[MAX_DATA_ARRAY]; /* data array */
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u8 wait_time; /* msec */
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u16 num_of_loops; /* for polling only */
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};
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/*
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* Sequence parameters. Each sequence contains:
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* 1. Sequence id.
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* 2. Sequence size (total amount of operations during the sequence)
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* 3. a series of operations. operations can be write, poll or delay
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* 4. index in the data array (the entry where the relevant data sits)
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*/
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struct cfg_seq {
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struct op_params *op_params_ptr;
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u8 cfg_seq_size;
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u8 data_arr_idx;
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};
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extern struct cfg_seq serdes_seq_db[];
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/*
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* A generic function type for executing an operation (write, poll or delay)
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*/
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typedef int (*op_execute_func_ptr)(u32 serdes_num, struct op_params *params,
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u32 data_arr_idx);
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/* Specific functions for executing each operation */
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int write_op_execute(u32 serdes_num, struct op_params *params,
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u32 data_arr_idx);
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int delay_op_execute(u32 serdes_num, struct op_params *params,
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u32 data_arr_idx);
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int poll_op_execute(u32 serdes_num, struct op_params *params, u32 data_arr_idx);
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enum mv_op get_cfg_seq_op(struct op_params *params);
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int mv_seq_exec(u32 serdes_num, u32 seq_id);
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#endif /*_SEQ_EXEC_H*/
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@ -1231,6 +1231,16 @@ static size_t image_headersz_v1(int *hasext)
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if (count > 0)
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headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
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/*
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* For all images except UART, headersz stored in header itself should
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* contains header size without padding. For UART image BootROM rounds
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* down headersz to multiply of 128 bytes. Therefore align UART headersz
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* to multiply of 128 bytes to ensure that remaining UART header bytes
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* are not ignored by BootROM.
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*/
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if (image_get_bootfrom() == IBR_HDR_UART_ID)
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headersz = ALIGN(headersz, 128);
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return headersz;
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}
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@ -61,7 +61,9 @@
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* SPI-NOR or parallel-NOR. Despite the type name it really can be stored on
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* parallel-NOR and cannot be stored on other SPI devices, like SPI-NAND.
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* So it should have been named NOR image, not SPI image. This image type
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* supports XIP - Execute In Place directly from NOR memory.
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* supports XIP - Execute In Place directly from NOR memory. Destination
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* address of the XIP image is set to 0xFFFFFFFF and execute address to the
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* absolute offset in bytes from the beginning of NOR memory.
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*
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* - IBR_HDR_NAND_ID (0x8B):
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* NAND image can be stored either at any 2 MB aligned offset in the first
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*
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* - IBR_HDR_UART_ID (0x69):
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* UART image can be transfered via xmodem protocol over first UART.
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* Unlike all other image types, header size stored in the image must be
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* multiply of the 128 bytes (for all other image types it can be any size)
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* and data part of the image does not have to contain 32-bit checksum
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* (all other image types must have valid 32-bit checksum in its data part).
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* And data size stored in the image is ignored. A38x BootROM determinates
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* size of the data part implicitly by the end of the xmodem transfer.
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* A38x BootROM has a bug which cause that BootROM loads data part of UART
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* image into RAM target address increased by one byte when source address
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* and header size stored in the image header are not same. So UART image
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* should be constructed in a way that there is no gap between header and
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* data part.
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*
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* - IBR_HDR_I2C_ID (0x4D):
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* It is unknown for what kind of storage is used this image. It is not
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@ -1455,6 +1468,8 @@ kwboot_xmodem(int tty, const void *_img, size_t size, int baudrate)
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* followed by the header. So align header size to xmodem block size.
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*/
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hdrsz += (KWBOOT_XM_BLKSZ - hdrsz % KWBOOT_XM_BLKSZ) % KWBOOT_XM_BLKSZ;
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if (hdrsz > size)
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hdrsz = size;
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pnum = 1;
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goto err;
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}
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kwboot_img_grow_data_right(img, size, sizeof(uint32_t));
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/* Update the 32-bit data checksum */
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*kwboot_img_csum32_ptr(img) = kwboot_img_csum32(img);
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}
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if (!kwboot_img_has_ddr_init(img) &&
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kwboot_printv("Aligning image header to Xmodem block size\n");
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kwboot_img_grow_hdr(img, size, grow);
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hdrsz += grow;
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/*
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* kwbimage v1 contains header size field and for UART type it
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* must be set to the aligned xmodem header size because BootROM
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* rounds header size down to xmodem block size.
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*/
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if (kwbimage_version(img) == 1) {
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hdr->headersz_msb = hdrsz >> 16;
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hdr->headersz_lsb = cpu_to_le16(hdrsz & 0xffff);
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}
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}
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/* Header size and source address must be same for UART type due to A38x BootROM bug */
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if (hdrsz != le32_to_cpu(hdr->srcaddr)) {
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if (is_secure) {
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fprintf(stderr, "Cannot align image with secure header\n");
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goto err;
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}
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kwboot_printv("Removing gap between image header and data\n");
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memmove(img + hdrsz, img + le32_to_cpu(hdr->srcaddr), le32_to_cpu(hdr->blocksize));
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hdr->srcaddr = cpu_to_le32(hdrsz);
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}
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hdr->checksum = kwboot_hdr_csum8(hdr) - csum;
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