mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mmc
* 'master' of git://git.denx.de/u-boot-mmc: ftsdc010: add support of ftsdc010 mmc controller mmc: Fix mmc_send_status()
This commit is contained in:
Wolfgang Denk
commit
49ea2e342b
4 changed files with 915 additions and 1 deletions
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@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
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COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
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COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
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COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
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COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
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COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
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COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
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COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
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667
drivers/mmc/ftsdc010_esdhc.c
Normal file
667
drivers/mmc/ftsdc010_esdhc.c
Normal file
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@ -0,0 +1,667 @@
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <faraday/ftsdc010.h>
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/*
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* supported mmc hosts
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* setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
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*/
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static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
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static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
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static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
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{
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return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
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}
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#ifdef DEBUG
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static void ftsdc010_dump_reg(struct mmc_host *host)
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{
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debug("cmd: %08x\n", readl(&host->reg->cmd));
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debug("argu: %08x\n", readl(&host->reg->argu));
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debug("rsp0: %08x\n", readl(&host->reg->rsp0));
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debug("rsp1: %08x\n", readl(&host->reg->rsp1));
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debug("rsp2: %08x\n", readl(&host->reg->rsp2));
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debug("rsp3: %08x\n", readl(&host->reg->rsp3));
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debug("rsp_cmd: %08x\n", readl(&host->reg->rsp_cmd));
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debug("dcr: %08x\n", readl(&host->reg->dcr));
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debug("dtr: %08x\n", readl(&host->reg->dtr));
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debug("dlr: %08x\n", readl(&host->reg->dlr));
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debug("status: %08x\n", readl(&host->reg->status));
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debug("clr: %08x\n", readl(&host->reg->clr));
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debug("int_mask: %08x\n", readl(&host->reg->int_mask));
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debug("pcr: %08x\n", readl(&host->reg->pcr));
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debug("ccr: %08x\n", readl(&host->reg->ccr));
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debug("bwr: %08x\n", readl(&host->reg->bwr));
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debug("dwr: %08x\n", readl(&host->reg->dwr));
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debug("feature: %08x\n", readl(&host->reg->feature));
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debug("rev: %08x\n", readl(&host->reg->rev));
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}
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#endif
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static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
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{
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unsigned int newmask;
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newmask = readl(®->int_mask);
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newmask |= imask;
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writel(newmask, ®->int_mask);
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return newmask;
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}
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static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
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{
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unsigned int fifo;
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unsigned int fifo_words;
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unsigned int *ptr;
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unsigned int status;
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unsigned int retry = 0;
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/* get_data_buffer */
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ptr = (unsigned int *)buf;
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while (size) {
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status = readl(&host->reg->status);
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if (status & FTSDC010_STATUS_FIFO_ORUN) {
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fifo = host->fifo_len > size ?
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size : host->fifo_len;
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size -= fifo;
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fifo_words = fifo >> 2;
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while (fifo_words--)
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*ptr++ = readl(&host->reg->dwr);
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/*
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* for adding some delays for SD card to put
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* data into FIFO again
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*/
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udelay(4*FTSDC010_DELAY_UNIT);
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#ifdef CONFIG_FTSDC010_SDIO
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/* sdio allow non-power-of-2 blksz */
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if (fifo & 3) {
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unsigned int n = fifo & 3;
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unsigned int data = readl(&host->reg->dwr);
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unsigned char *p = (unsigned char *)ptr;
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while (n--) {
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*p++ = data;
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data >>= 8;
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}
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}
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#endif
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} else {
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udelay(1);
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if (++retry >= FTSDC010_PIO_RETRY) {
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debug("%s: PIO_RETRY timeout\n", __func__);
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return;
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}
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}
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}
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}
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static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
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unsigned int size)
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{
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unsigned int fifo;
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unsigned int *ptr;
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unsigned int status;
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unsigned int retry = 0;
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/* get data buffer */
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ptr = (unsigned int *)buf;
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while (size) {
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status = readl(&host->reg->status);
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if (status & FTSDC010_STATUS_FIFO_ORUN) {
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fifo = host->fifo_len > size ?
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size : host->fifo_len;
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size -= fifo;
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fifo = (fifo + 3) >> 2;
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while (fifo--) {
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writel(*ptr, &host->reg->dwr);
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ptr++;
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}
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} else {
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udelay(1);
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if (++retry >= FTSDC010_PIO_RETRY) {
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debug("%s: PIO_RETRY timeout\n", __func__);
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return;
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}
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}
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}
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}
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static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int sta, clear;
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unsigned int i;
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/* check response and hardware status */
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clear = 0;
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/* chech CMD_SEND */
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for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
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sta = readl(&host->reg->status);
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/* Command Complete */
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if (sta & FTSDC010_STATUS_CMD_SEND) {
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if (!data)
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clear |= FTSDC010_CLR_CMD_SEND;
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break;
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}
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}
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if (i > FTSDC010_CMD_RETRY) {
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printf("%s: send command timeout\n", __func__);
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return TIMEOUT;
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}
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/* debug: print status register and command index*/
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debug("sta: %08x cmd %d\n", sta, cmd->cmdidx);
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/* handle data FIFO */
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if ((sta & FTSDC010_STATUS_FIFO_ORUN) ||
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(sta & FTSDC010_STATUS_FIFO_URUN)) {
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/* Wrong DATA FIFO Flag */
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if (data == NULL)
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printf("%s, data fifo wrong: sta: %08x cmd %d\n",
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__func__, sta, cmd->cmdidx);
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if (sta & FTSDC010_STATUS_FIFO_ORUN)
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clear |= FTSDC010_STATUS_FIFO_ORUN;
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if (sta & FTSDC010_STATUS_FIFO_URUN)
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clear |= FTSDC010_STATUS_FIFO_URUN;
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}
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/* check RSP TIMEOUT or FAIL */
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if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
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/* RSP TIMEOUT */
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debug("%s: RSP timeout: sta: %08x cmd %d\n",
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__func__, sta, cmd->cmdidx);
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clear |= FTSDC010_CLR_RSP_TIMEOUT;
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writel(clear, &host->reg->clr);
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return TIMEOUT;
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} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
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/* clear response fail bit */
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debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n",
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__func__, sta, cmd->cmdidx);
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clear |= FTSDC010_CLR_RSP_CRC_FAIL;
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writel(clear, &host->reg->clr);
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return 0;
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} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
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/* clear response CRC OK bit */
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clear |= FTSDC010_CLR_RSP_CRC_OK;
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}
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/* check DATA TIMEOUT or FAIL */
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if (data) {
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if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
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/* DATA TIMEOUT */
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debug("%s: DATA TIMEOUT: sta: %08x\n",
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__func__, sta);
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clear |= FTSDC010_STATUS_DATA_TIMEOUT;
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writel(sta, &host->reg->clr);
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return TIMEOUT;
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} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
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/* Error Interrupt */
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debug("%s: DATA CRC FAIL: sta: %08x\n",
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__func__, sta);
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clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
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writel(clear, &host->reg->clr);
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return 0;
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} else if (sta & FTSDC010_STATUS_DATA_END) {
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/* Transfer Complete */
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clear |= FTSDC010_STATUS_DATA_END;
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}
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}
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/* transaction is success and clear status register */
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writel(clear, &host->reg->clr);
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return 0;
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}
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static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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#ifdef CONFIG_FTSDC010_SDIO
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unsigned int scon;
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#endif
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unsigned int ccon;
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unsigned int mask, tmpmask;
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unsigned int ret;
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if (data)
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
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else
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mask = FTSDC010_INT_MASK_CMD_SEND;
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/* write argu reg */
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debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg);
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writel(cmd->cmdarg, &host->reg->argu);
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/* setup cmd reg */
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debug("cmd: %d\n", cmd->cmdidx);
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debug("resp: %08x\n", cmd->resp_type);
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/* setup commnad */
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ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
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/* setup command flags */
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ccon |= FTSDC010_CMD_CMD_EN;
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/*
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* This hardware didn't support specific commands for mapping
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* MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
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*/
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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ccon |= FTSDC010_CMD_NEED_RSP;
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mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
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FTSDC010_INT_MASK_RSP_CRC_FAIL;
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}
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if (cmd->resp_type & MMC_RSP_136)
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ccon |= FTSDC010_CMD_LONG_RSP;
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/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
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if (host->last_opcode == MMC_CMD_APP_CMD)
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ccon |= FTSDC010_CMD_APP_CMD;
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#ifdef CONFIG_FTSDC010_SDIO
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scon = readl(&host->reg->sdio_ctrl1);
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if (host->card_type == MMC_TYPE_SDIO)
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scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
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else
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scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
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writel(scon, &host->reg->sdio_ctrl1);
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#endif
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/* record last opcode for specifing the command type to hardware */
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host->last_opcode = cmd->cmdidx;
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/* write int_mask reg */
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tmpmask = readl(&host->reg->int_mask);
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tmpmask |= mask;
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writel(tmpmask, &host->reg->int_mask);
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/* write cmd reg */
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debug("%s: ccon: %08x\n", __func__, ccon);
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writel(ccon, &host->reg->cmd);
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udelay(4*FTSDC010_DELAY_UNIT);
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/* read/write data */
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if (data && (data->flags & MMC_DATA_READ)) {
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ftsdc010_pio_read(host, data->dest,
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data->blocksize * data->blocks);
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} else if (data && (data->flags & MMC_DATA_WRITE)) {
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ftsdc010_pio_write(host, data->src,
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data->blocksize * data->blocks);
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}
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/* pio check response status */
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ret = ftsdc010_pio_check_status(mmc, cmd, data);
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if (!ret) {
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/* if it is long response */
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if (ccon & FTSDC010_CMD_LONG_RSP) {
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cmd->response[0] = readl(&host->reg->rsp3);
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cmd->response[1] = readl(&host->reg->rsp2);
|
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cmd->response[2] = readl(&host->reg->rsp1);
|
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cmd->response[3] = readl(&host->reg->rsp0);
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|
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} else {
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cmd->response[0] = readl(&host->reg->rsp0);
|
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}
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}
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|
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udelay(FTSDC010_DELAY_UNIT);
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return ret;
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}
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|
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static unsigned int cal_blksz(unsigned int blksz)
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{
|
||||
unsigned int blksztwo = 0;
|
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|
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while (blksz >>= 1)
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blksztwo++;
|
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|
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return blksztwo;
|
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}
|
||||
|
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static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
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unsigned int dcon, newmask;
|
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|
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/* configure data transfer paramter */
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if (!data)
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return 0;
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|
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if (((data->blocksize - 1) & data->blocksize) != 0) {
|
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printf("%s: can't do non-power-of 2 sized block transfers"
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" (blksz %d)\n", __func__, data->blocksize);
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return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* We cannot deal with unaligned blocks with more than
|
||||
* one block being transfered.
|
||||
*/
|
||||
if ((data->blocksize <= 2) && (data->blocks > 1)) {
|
||||
printf("%s: can't do non-word sized block transfers"
|
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" (blksz %d)\n", __func__, data->blocksize);
|
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return -1;
|
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}
|
||||
|
||||
/* data length */
|
||||
dcon = data->blocksize * data->blocks;
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writel(dcon, &host->reg->dlr);
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/* write data control */
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dcon = cal_blksz(data->blocksize);
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/* add to IMASK register */
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newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
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|
||||
/*
|
||||
* enable UNDERRUN will trigger interrupt immediatedly
|
||||
* So setup it when rsp is received successfully
|
||||
*/
|
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if (data->flags & MMC_DATA_WRITE) {
|
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dcon |= FTSDC010_DCR_DATA_WRITE;
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} else {
|
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dcon &= ~FTSDC010_DCR_DATA_WRITE;
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newmask |= FTSDC010_STATUS_FIFO_ORUN;
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}
|
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enable_imask(host->reg, newmask);
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||||
|
||||
#ifdef CONFIG_FTSDC010_SDIO
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/* always reset fifo since last transfer may fail */
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dcon |= FTSDC010_DCR_FIFO_RST;
|
||||
|
||||
/* handle sdio */
|
||||
dcon = data->blocksize | data->blocks << 15;
|
||||
if (data->blocks > 1)
|
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dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
|
||||
#endif
|
||||
|
||||
/* enable data transfer which will be pended until cmd is send */
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dcon |= FTSDC010_DCR_DATA_EN;
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||||
writel(dcon, &host->reg->dcr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
|
||||
struct mmc_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (data) {
|
||||
ret = ftsdc010_setup_data(mmc, data);
|
||||
|
||||
if (ret) {
|
||||
printf("%s: setup data error\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
|
||||
printf("%s: data is both direction\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Send command */
|
||||
ret = ftsdc010_send_cmd(mmc, cmd, data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ftsdc010_card_detect(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
||||
unsigned int sta;
|
||||
|
||||
sta = readl(&host->reg->status);
|
||||
debug("%s: card status: %08x\n", __func__, sta);
|
||||
|
||||
return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
|
||||
}
|
||||
|
||||
static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
|
||||
struct mmc_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (ftsdc010_card_detect(mmc) == 0) {
|
||||
printf("%s: no medium present\n", __func__);
|
||||
return -1;
|
||||
} else {
|
||||
ret = ftsdc010_send_request(mmc, cmd, data);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
static void ftsdc010_set_clk(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
||||
unsigned char clk_div;
|
||||
unsigned char real_rate;
|
||||
unsigned int clock;
|
||||
|
||||
debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
|
||||
clock = readl(&host->reg->ccr);
|
||||
|
||||
if (mmc->clock == 0) {
|
||||
real_rate = 0;
|
||||
clock |= FTSDC010_CCR_CLK_DIS;
|
||||
} else {
|
||||
debug("%s, mmc->clock: %08x, origin clock: %08x\n",
|
||||
__func__, mmc->clock, clock);
|
||||
|
||||
for (clk_div = 0; clk_div <= 127; clk_div++) {
|
||||
real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
|
||||
(2 * (clk_div + 1));
|
||||
|
||||
if (real_rate <= mmc->clock)
|
||||
break;
|
||||
}
|
||||
|
||||
debug("%s: computed real_rete: %x, clk_div: %x\n",
|
||||
__func__, real_rate, clk_div);
|
||||
|
||||
if (clk_div > 127)
|
||||
debug("%s: no match clock rate, %x\n",
|
||||
__func__, mmc->clock);
|
||||
|
||||
clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
|
||||
FTSDC010_CCR_CLK_DIV(clk_div);
|
||||
|
||||
clock &= ~FTSDC010_CCR_CLK_DIS;
|
||||
}
|
||||
|
||||
debug("%s, set clock: %08x\n", __func__, clock);
|
||||
writel(clock, &host->reg->ccr);
|
||||
}
|
||||
|
||||
static void ftsdc010_set_ios(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
||||
unsigned int power;
|
||||
unsigned long val;
|
||||
unsigned int bus_width;
|
||||
|
||||
debug("%s: bus_width: %x, clock: %d\n",
|
||||
__func__, mmc->bus_width, mmc->clock);
|
||||
|
||||
/* set pcr: power on */
|
||||
power = readl(&host->reg->pcr);
|
||||
power |= FTSDC010_PCR_POWER_ON;
|
||||
writel(power, &host->reg->pcr);
|
||||
|
||||
if (mmc->clock)
|
||||
ftsdc010_set_clk(mmc);
|
||||
|
||||
/* set bwr: bus width reg */
|
||||
bus_width = readl(&host->reg->bwr);
|
||||
bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
|
||||
FTSDC010_BWR_SINGLE_BUS);
|
||||
|
||||
if (mmc->bus_width == 8)
|
||||
bus_width |= FTSDC010_BWR_WIDE_8_BUS;
|
||||
else if (mmc->bus_width == 4)
|
||||
bus_width |= FTSDC010_BWR_WIDE_4_BUS;
|
||||
else
|
||||
bus_width |= FTSDC010_BWR_SINGLE_BUS;
|
||||
|
||||
writel(bus_width, &host->reg->bwr);
|
||||
|
||||
/* set fifo depth */
|
||||
val = readl(&host->reg->feature);
|
||||
host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
|
||||
|
||||
/* set data timeout register */
|
||||
val = -1;
|
||||
writel(val, &host->reg->dtr);
|
||||
}
|
||||
|
||||
static void ftsdc010_reset(struct mmc_host *host)
|
||||
{
|
||||
unsigned int timeout;
|
||||
|
||||
/* Do SDC_RST: Software reset for all register */
|
||||
writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
|
||||
|
||||
host->clock = 0;
|
||||
|
||||
/* this hardware has no reset finish flag to read */
|
||||
/* wait 100ms maximum */
|
||||
timeout = 100;
|
||||
|
||||
/* hw clears the bit when it's done */
|
||||
while (readl(&host->reg->dtr) != 0) {
|
||||
if (timeout == 0) {
|
||||
printf("%s: reset timeout error\n", __func__);
|
||||
return;
|
||||
}
|
||||
timeout--;
|
||||
udelay(10*FTSDC010_DELAY_UNIT);
|
||||
}
|
||||
}
|
||||
|
||||
static int ftsdc010_core_init(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
||||
unsigned int mask;
|
||||
unsigned int major, minor, revision;
|
||||
|
||||
/* get hardware version */
|
||||
host->version = readl(&host->reg->rev);
|
||||
|
||||
major = FTSDC010_REV_MAJOR(host->version);
|
||||
minor = FTSDC010_REV_MINOR(host->version);
|
||||
revision = FTSDC010_REV_REVISION(host->version);
|
||||
|
||||
printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
|
||||
|
||||
/* Interrupt MASK register init - mask all */
|
||||
writel(0x0, &host->reg->int_mask);
|
||||
|
||||
mask = FTSDC010_INT_MASK_CMD_SEND |
|
||||
FTSDC010_INT_MASK_DATA_END |
|
||||
FTSDC010_INT_MASK_CARD_CHANGE;
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
mask |= FTSDC010_INT_MASK_CP_READY |
|
||||
FTSDC010_INT_MASK_CP_BUF_READY |
|
||||
FTSDC010_INT_MASK_PLAIN_TEXT_READY |
|
||||
FTSDC010_INT_MASK_SDIO_IRPT;
|
||||
#endif
|
||||
|
||||
writel(mask, &host->reg->int_mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ftsdc010_mmc_init(int dev_index)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
struct mmc_host *host;
|
||||
|
||||
mmc = &ftsdc010_dev[dev_index];
|
||||
|
||||
sprintf(mmc->name, "FTSDC010 SD/MMC");
|
||||
mmc->priv = &ftsdc010_host[dev_index];
|
||||
mmc->send_cmd = ftsdc010_request;
|
||||
mmc->set_ios = ftsdc010_set_ios;
|
||||
mmc->init = ftsdc010_core_init;
|
||||
|
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
|
||||
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
||||
|
||||
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||||
|
||||
mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
|
||||
mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
|
||||
|
||||
ftsdc010_host[dev_index].clock = 0;
|
||||
ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
|
||||
mmc_register(mmc);
|
||||
|
||||
/* reset mmc */
|
||||
host = (struct mmc_host *)mmc->priv;
|
||||
ftsdc010_reset(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -115,7 +115,8 @@ int mmc_send_status(struct mmc *mmc, int timeout)
|
|||
|
||||
cmd.cmdidx = MMC_CMD_SEND_STATUS;
|
||||
cmd.resp_type = MMC_RSP_R1;
|
||||
cmd.cmdarg = 0;
|
||||
if (!mmc_host_is_spi(mmc))
|
||||
cmd.cmdarg = mmc->rca << 16;
|
||||
cmd.flags = 0;
|
||||
|
||||
do {
|
||||
|
|
|
|||
245
include/faraday/ftsdc010.h
Normal file
245
include/faraday/ftsdc010.h
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
/*
|
||||
* Faraday FTSDC010 Secure Digital Memory Card Host Controller
|
||||
*
|
||||
* Copyright (C) 2011 Andes Technology Corporation
|
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __FTSDC010_H
|
||||
#define __FTSDC010_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* sd controller register */
|
||||
struct ftsdc010_mmc {
|
||||
unsigned int cmd; /* 0x00 - command reg */
|
||||
unsigned int argu; /* 0x04 - argument reg */
|
||||
unsigned int rsp0; /* 0x08 - response reg0 */
|
||||
unsigned int rsp1; /* 0x0c - response reg1 */
|
||||
unsigned int rsp2; /* 0x10 - response reg2 */
|
||||
unsigned int rsp3; /* 0x14 - response reg3 */
|
||||
unsigned int rsp_cmd; /* 0x18 - responded cmd reg */
|
||||
unsigned int dcr; /* 0x1c - data control reg */
|
||||
unsigned int dtr; /* 0x20 - data timer reg */
|
||||
unsigned int dlr; /* 0x24 - data length reg */
|
||||
unsigned int status; /* 0x28 - status reg */
|
||||
unsigned int clr; /* 0x2c - clear reg */
|
||||
unsigned int int_mask; /* 0x30 - intrrupt mask reg */
|
||||
unsigned int pcr; /* 0x34 - power control reg */
|
||||
unsigned int ccr; /* 0x38 - clock contorl reg */
|
||||
unsigned int bwr; /* 0x3c - bus width reg */
|
||||
unsigned int dwr; /* 0x40 - data window reg */
|
||||
#ifndef CONFIG_FTSDC010_SDIO
|
||||
unsigned int feature; /* 0x44 - feature reg */
|
||||
unsigned int rev; /* 0x48 - revision reg */
|
||||
#else
|
||||
unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */
|
||||
unsigned int gpo; /* 0x48 - gerenal purpose output */
|
||||
unsigned int reserved[8]; /* 0x50 - 0x68 reserved */
|
||||
unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */
|
||||
unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */
|
||||
unsigned int sdio_status; /* 0x74 - SDIO status regi */
|
||||
unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */
|
||||
unsigned int feature; /* 0x9c - feature reg */
|
||||
unsigned int rev; /* 0xa0 - revision reg */
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
};
|
||||
|
||||
struct mmc_host {
|
||||
struct ftsdc010_mmc *reg;
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
unsigned int fifo_len; /* bytes */
|
||||
unsigned int last_opcode; /* Last OP Code */
|
||||
unsigned int card_type; /* Card type */
|
||||
};
|
||||
|
||||
/* functions */
|
||||
int ftsdc010_mmc_init(int dev_index);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* global defines */
|
||||
#define FTSDC010_CMD_RETRY 0x100000
|
||||
#define FTSDC010_PIO_RETRY 100 /* pio retry times */
|
||||
#define FTSDC010_DELAY_UNIT 100 /* 100 us */
|
||||
|
||||
/* define from Linux kernel - include/linux/mmc/card.h */
|
||||
#define MMC_TYPE_SDIO 2 /* SDIO card */
|
||||
|
||||
/* define for mmc layer */
|
||||
#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
|
||||
|
||||
/* this part is strange */
|
||||
#define FTSDC010_SDIO_CTRL1_REG 0x0000006C
|
||||
#define FTSDC010_SDIO_CTRL2_REG 0x0000006C
|
||||
#define FTSDC010_SDIO_STATUS_REG 0x00000070
|
||||
|
||||
/* 0x00 - command register */
|
||||
#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0)
|
||||
#define FTSDC010_CMD_NEED_RSP (1 << 6)
|
||||
#define FTSDC010_CMD_LONG_RSP (1 << 7)
|
||||
#define FTSDC010_CMD_APP_CMD (1 << 8)
|
||||
#define FTSDC010_CMD_CMD_EN (1 << 9)
|
||||
#define FTSDC010_CMD_SDC_RST (1 << 10)
|
||||
#define FTSDC010_CMD_MMC_INT_STOP (1 << 11)
|
||||
|
||||
/* 0x18 - responded command register */
|
||||
#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f)
|
||||
#define FTSDC010_RSP_CMD_APP (1 << 6)
|
||||
|
||||
/* 0x1c - data control register */
|
||||
#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0)
|
||||
#define FTSDC010_DCR_DATA_WRITE (1 << 4)
|
||||
#define FTSDC010_DCR_DMA_EN (1 << 5)
|
||||
#define FTSDC010_DCR_DATA_EN (1 << 6)
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
#define FTSDC010_DCR_FIFOTH (1 << 7)
|
||||
#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8)
|
||||
#define FTSDC010_DCR_FIFO_RST (1 << 10)
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
|
||||
#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */
|
||||
#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */
|
||||
#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */
|
||||
|
||||
#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */
|
||||
|
||||
/* CPRM related define */
|
||||
#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008
|
||||
#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010
|
||||
|
||||
/* 0x28 - status register */
|
||||
#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0)
|
||||
#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1)
|
||||
#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2)
|
||||
#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3)
|
||||
#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4)
|
||||
#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5)
|
||||
#define FTSDC010_STATUS_CMD_SEND (1 << 6)
|
||||
#define FTSDC010_STATUS_DATA_END (1 << 7)
|
||||
#define FTSDC010_STATUS_FIFO_URUN (1 << 8)
|
||||
#define FTSDC010_STATUS_FIFO_ORUN (1 << 9)
|
||||
#define FTSDC010_STATUS_CARD_CHANGE (1 << 10)
|
||||
#define FTSDC010_STATUS_CARD_DETECT (1 << 11)
|
||||
#define FTSDC010_STATUS_WRITE_PROT (1 << 12)
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */
|
||||
#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */
|
||||
#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */
|
||||
#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */
|
||||
#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
|
||||
/* 0x2c - clear register */
|
||||
#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0)
|
||||
#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1)
|
||||
#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2)
|
||||
#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3)
|
||||
#define FTSDC010_CLR_RSP_CRC_OK (1 << 4)
|
||||
#define FTSDC010_CLR_DATA_CRC_OK (1 << 5)
|
||||
#define FTSDC010_CLR_CMD_SEND (1 << 6)
|
||||
#define FTSDC010_CLR_DATA_END (1 << 7)
|
||||
#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */
|
||||
#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */
|
||||
#define FTSDC010_CLR_CARD_CHANGE (1 << 10)
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
#define FTSDC010_CLR_SDIO_IRPT (1 << 16)
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
|
||||
/* 0x30 - interrupt mask register */
|
||||
#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0)
|
||||
#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1)
|
||||
#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2)
|
||||
#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3)
|
||||
#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4)
|
||||
#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5)
|
||||
#define FTSDC010_INT_MASK_CMD_SEND (1 << 6)
|
||||
#define FTSDC010_INT_MASK_DATA_END (1 << 7)
|
||||
#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8)
|
||||
#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9)
|
||||
#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10)
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
#define FTSDC010_INT_MASK_CP_READY (1 << 13)
|
||||
#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14)
|
||||
#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15)
|
||||
#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16)
|
||||
#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
|
||||
/* ? */
|
||||
#define FTSDC010_CARD_INSERT 0x0
|
||||
#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT
|
||||
|
||||
/* 0x34 - power control register */
|
||||
#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0)
|
||||
#define FTSDC010_PCR_POWER_ON (1 << 4)
|
||||
|
||||
/* 0x38 - clock control register */
|
||||
#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0)
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#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */
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#define FTSDC010_CCR_CLK_DIS (1 << 8)
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/* card type */
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||||
#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE
|
||||
#define FTSDC010_CARD_TYPE_MMC 0x0
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||||
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||||
/* 0x3c - bus width register */
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||||
#define FTSDC010_BWR_SINGLE_BUS (1 << 0)
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#define FTSDC010_BWR_WIDE_8_BUS (1 << 1)
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#define FTSDC010_BWR_WIDE_4_BUS (1 << 2)
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#define FTSDC010_BWR_WIDE_BUS_SUPPORT(x) (((x) >> 3) & 0x3)
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#define FTSDC010_BWR_CARD_DETECT (1 << 5)
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#define FTSDC010_BWR_1_BUS_SUPPORT 0x0
|
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#define FTSDC010_BWR_4_BUS_SUPPORT 0x1
|
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#define FTSDC010_BWR_8_BUS_SUPPORT 0x2
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||||
/* 0x44 or 0x9c - feature register */
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||||
#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff)
|
||||
#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8)
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||||
|
||||
#define FTSDC010_FIFO_DEPTH_4 0x04
|
||||
#define FTSDC010_FIFO_DEPTH_8 0x08
|
||||
#define FTSDC010_FIFO_DEPTH_16 0x10
|
||||
|
||||
/* 0x48 or 0xa0 - revision register */
|
||||
#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0)
|
||||
#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8)
|
||||
#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16)
|
||||
|
||||
#ifdef CONFIG_FTSDC010_SDIO
|
||||
/* 0x44 - general purpose output */
|
||||
#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* 0x6c - sdio control register 1 */
|
||||
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0)
|
||||
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12)
|
||||
#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13)
|
||||
#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14)
|
||||
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15)
|
||||
|
||||
/* 0x70 - sdio control register 2 */
|
||||
#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0)
|
||||
#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1)
|
||||
|
||||
/* 0x74 - sdio status register */
|
||||
#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff)
|
||||
#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef)
|
||||
|
||||
#endif /* CONFIG_FTSDC010_SDIO */
|
||||
|
||||
#endif /* __FTSDC010_H */
|
||||
Loading…
Reference in a new issue