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armv8: ls1088a: Enable PCIe in defconfigs
Enabled PCIe support and PCI command feature. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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commit
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3 changed files with 12 additions and 0 deletions
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@ -22,6 +22,10 @@ CONFIG_DM=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_NETDEVICES=y
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CONFIG_E1000=y
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CONFIG_E1000=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYS_NS16550=y
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CONFIG_FSL_DSPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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@ -22,6 +22,10 @@ CONFIG_DM=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_NETDEVICES=y
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CONFIG_E1000=y
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CONFIG_E1000=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYS_NS16550=y
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CONFIG_FSL_DSPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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@ -44,6 +44,10 @@
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*/
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*/
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#define CPU_RELEASE_ADDR secondary_boot_func
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#define CPU_RELEASE_ADDR secondary_boot_func
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#endif
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/* Size of malloc() pool */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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