Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 08:01:08 +00:00
Code Issues Projects Releases Packages Wiki Activity

x86: Fix MTRR clear to detect which MTRR to use

Browse source 
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Duncan Laurie 2012-12-03 13:59:00 +00:00 committed by Simon Glass
parent 300081aa68
commit 488b8b242b
1 changed files with 15 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
arch/x86/cpu/coreboot/coreboot.c
View file

@ -94,6 +94,8 @@ void setup_pcat_compatibility()
{ {
} }
#define MTRR_TYPE_WP 5
#define MTRRcap_MSR 0xfe
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
@ -101,11 +103,20 @@ int board_final_cleanup(void)
{ {
/* Un-cache the ROM so the kernel has one /* Un-cache the ROM so the kernel has one
* more MTRR available. * more MTRR available.
*
* Coreboot should have assigned this to the
* top available variable MTRR.
*/ */
disable_caches(); u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
wrmsrl(MTRRphysBase_MSR(7), 0); u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
wrmsrl(MTRRphysMask_MSR(7), 0);
enable_caches(); /* Make sure this MTRR is the correct Write-Protected type */
if (top_type == MTRR_TYPE_WP) {
disable_caches();
wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
enable_caches();
}
return 0; return 0;
} }