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Blackfin: update anomaly lists
Update the anomaly lists to match latest anomaly sheets. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
9d8811c5bd
commit
47832cd15a
5 changed files with 213 additions and 84 deletions
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@ -7,82 +7,154 @@
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*/
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/* This file shoule be up to date with:
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* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
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* - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
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# define ANOMALY_BF526 1
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#else
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# define ANOMALY_BF526 0
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#endif
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#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
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# define ANOMALY_BF527 1
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#else
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# define ANOMALY_BF527 0
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (1)
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#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (1)
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#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (1)
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#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (1)
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#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (1)
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#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* USB Calibration Value to use */
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#define ANOMALY_05000346_value 0xE510
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Security Features Are Not Functional */
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#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
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#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
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#define ANOMALY_05000353 (ANOMALY_BF526)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
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#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* New Feature: Higher Default CCLK Rate */
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#define ANOMALY_05000368 (1)
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/* Incorrect Default CSEL Value in PLL_DIV */
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#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Authentication Fails To Initiate */
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#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
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#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Data Read From L3 Memory by USB DMA May be Corrupted */
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#define ANOMALY_05000380 (1)
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/* USB Full-speed Mode not Fully Tested */
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#define ANOMALY_05000381 (1)
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/* New Feature: Boot from OTP Memory */
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#define ANOMALY_05000385 (1)
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/* New Feature: bfrom_SysControl() Routine */
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#define ANOMALY_05000386 (1)
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/* New Feature: Programmable Preboot Settings */
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#define ANOMALY_05000387 (1)
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#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* 8-Bit NAND Flash Boot Mode Not Functional */
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#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
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/* Host Must Not Read Back During Host DMA Boot */
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#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Boot from OTP Memory Not Functional */
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#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* bfrom_SysControl() Firmware Routine Not Functional */
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#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Programmable Preboot Settings Not Functional */
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#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* CRC32 Checksum Support Not Functional */
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#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (1)
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/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (1)
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/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (1)
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/* New Feature: Log Buffer Functionality */
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#define ANOMALY_05000394 (1)
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/* New Feature: Hook Routine Functionality */
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#define ANOMALY_05000395 (1)
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/* New Feature: Header Indirect Bit */
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#define ANOMALY_05000396 (1)
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/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
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#define ANOMALY_05000397 (1)
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/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
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#define ANOMALY_05000398 (1)
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/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
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#define ANOMALY_05000399 (1)
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#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Log Buffer Not Functional */
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#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Hook Routine Not Functional */
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#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Header Indirect Bit Not Functional */
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#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
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#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
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#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
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#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
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#define ANOMALY_05000401 (1)
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#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
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/* Lockbox SESR Disallows Certain User Interrupts */
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#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
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#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Lockbox firmware leaves MDMA0 channel enabled */
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#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
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/* Incorrect Default Internal Voltage Regulator Setting */
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#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
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/* DEB2_URGENT Bit Not Functional */
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#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
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#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
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#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
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/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
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#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
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/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
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#define ANOMALY_05000421 (1)
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/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
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#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
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/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
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#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
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/* Internal Voltage Regulator Not Trimmed */
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#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
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#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
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/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
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#define ANOMALY_05000432 (ANOMALY_BF526)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000412 (0)
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#endif
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*/
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/* This file shoule be up to date with:
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* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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* - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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/* UART STB Bit Incorrectly Affects Receiver Setting */
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#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
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/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
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#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
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#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
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/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
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#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
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#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
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#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
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#define ANOMALY_05000265 (1)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
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#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (1)
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
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/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
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#define ANOMALY_05000276 (1)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (1)
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (1)
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
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/* False Hardware Error Exception When ISR Context Is Not Restored */
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#define ANOMALY_05000281 (1)
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (1)
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
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/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
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#define ANOMALY_05000283 (1)
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#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
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/* SPORTs May Receive Bad Data If FIFOs Fill Up */
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#define ANOMALY_05000288 (1)
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#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
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/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
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#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
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#define ANOMALY_05000311 (1)
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#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
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/* PPI Is Level-Sensitive on First Transfer */
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#define ANOMALY_05000313 (1)
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
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/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
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#define ANOMALY_05000315 (1)
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
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/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
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#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
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#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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||||
#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
|
||||
/* PPI Does Not Start Properly In Specific Mode */
|
||||
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
|
||||
#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
|
|
@ -271,5 +278,9 @@
|
|||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -148,6 +148,14 @@
|
|||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
|
@ -160,5 +168,9 @@
|
|||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
/* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
|
||||
/* External FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
|
|
@ -61,6 +61,8 @@
|
|||
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value Is Not Intialized */
|
||||
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value to use */
|
||||
#define ANOMALY_05000346_value 0x5411
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost when Core Reads SDH Data FIFO */
|
||||
|
|
@ -68,7 +70,7 @@
|
|||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
|
|
@ -86,13 +88,13 @@
|
|||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* Mobile DDR Operation Not Functional */
|
||||
#define ANOMALY_05000377 (1)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (1)
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
|
|
@ -126,25 +128,37 @@
|
|||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (1)
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (1)
|
||||
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (1)
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (1)
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (1)
|
||||
/* FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000412 (1)
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (1)
|
||||
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (1)
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
||||
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
|
|
@ -161,5 +175,8 @@
|
|||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
* - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
|
|
@ -264,6 +264,18 @@
|
|||
#define ANOMALY_05000371 (1)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
|
||||
#define ANOMALY_05000412 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
|
||||
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000158 (0)
|
||||
|
|
@ -271,5 +283,8 @@
|
|||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue