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Merge tag 'rockchip-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse source 
- Fix rk3368 lion board support;
- Fix px30 odroid-go2 board support;
- Add rk3399 NanoPi R4s and NanoPi M4B board support;
This commit is contained in:
Tom Rini 2021-04-05 22:39:10 -04:00
commit 472fd5a35a
26 changed files with 1135 additions and 327 deletions
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4
arch/arm/dts/Makefile
View file

@ -114,7 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion.dtb \
rk3368-lion-haikou.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
@ -131,7 +131,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-m4b.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-nanopi-r4s.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
rk3399-puma-haikou.dtb \

2
arch/arm/dts/rk3368-geekbox-u-boot.dtsi
View file

@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include "rk3368-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};

6
arch/arm/dts/rk3368-lion-u-boot.dtsi → arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi
View file

@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include "rk3368-u-boot.dtsi"
/ {
config {
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
@ -36,6 +38,10 @@
};
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

140
arch/arm/dts/rk3368-lion-haikou.dts Normal file
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@ -0,0 +1,140 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
*/
/dts-v1/;
#include "rk3368-lion.dtsi"
/ {
model = "Theobroma Systems RK3368-uQ7 Baseboard";
compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
chosen {
stdout-path = "serial0:115200n8";
};
i2cmux2 {
i2c@0 {
eeprom: eeprom@50 {
compatible = "atmel,24c01";
pagesize = <8>;
reg = <0x50>;
};
};
};
leds {
pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
sd_card_led: led-3 {
label = "sd_card_led";
gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_baseboard: vcc3v3-baseboard {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_baseboard";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
regulator-always-on;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc3v3_baseboard>;
status = "okay";
};
&spi2 {
cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};
&uart1 {
/* alternate function of GPIO5/6 */
status = "disabled";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&haikou_pin_hog>;
hog {
haikou_pin_hog: haikou-pin-hog {
rockchip,pins =
/* LID_BTN */
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
/* BATLOW# */
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
/* SLP_BTN# */
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
/* BIOS_DISABLE# */
<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
sd_card_led_pin: sd-card-led-pin {
rockchip,pins =
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_cd_pin: sdmmc-cd-pin {
rockchip,pins =
<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_otg {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins =
<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

271
arch/arm/dts/rk3368-lion.dts → arch/arm/dts/rk3368-lion.dtsi
View file

@ -1,25 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
* Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
*/
/dts-v1/;
#include "rk3368.dtsi"
#include "rk3368-lion-u-boot.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Theobroma Systems RK3368-uQ7 SoM";
compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
chosen {
stdout-path = "serial0:115200n8";
};
ext_gmac: gmac-clk {
@ -29,6 +18,80 @@
#clock-cells = <0>;
};
i2cmux1 {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c1>;
mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
/* Q7_GPO_I2C */
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* Q7_SMB */
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
i2cmux2 {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c2>;
mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
/* Q7_LVDS_BLC_I2C */
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#cooling-cells = <2>;
};
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
/* Q7_GP2_I2C */
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&module_led_pins>;
module_led1: led-1 {
label = "module_led1";
gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
module_led2: led-2 {
label = "module_led2";
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@ -39,43 +102,81 @@
};
};
&uart0 {
status = "okay";
&cpu_l0 {
cpu-supply = <&vdd_cpu>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu>;
};
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
mmc-hs200-1_8v;
non-removable;
num-slots = <1>;
vmmc-supply = <&vcc33_io>;
vqmmc-supply = <&vcc18_io>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
};
&sdmmc {
status = "okay";
};
&gmac {
status = "okay";
phy-supply = <&vcc33_io>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
phy-handle = <&phy0>;
phy-supply = <&vcc33_io>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
/* Microsemi VSC8531-02 */
phy0: phy@0 {
compatible = "ethernet-phy-id0007.0570";
reg = <0>;
vsc8531,clk-out-frequency = <125000000>;
vsc8531,edge-slowdown = <7>;
vsc8531,led-0-mode = <1>;
vsc8531,led-1-mode = <2>;
};
};
};
&i2c0 {
@ -85,7 +186,11 @@
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "xin32k", "rk808-clkout2";
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
@ -98,97 +203,129 @@
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_sys>;
clock-output-names = "xin32k", "rk808-clkout2";
#clock-cells = <1>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
};
vdd_log: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_log";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
};
vcc33_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_io";
regulator-always-on;
regulator-boot-on;
};
vcc33_video: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_video";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_video";
regulator-always-on;
regulator-boot-on;
};
vdd10_pll: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd10_pll";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_pll";
regulator-always-on;
regulator-boot-on;
};
vcc18_io: LDO_REG4 {
regulator-boot-on;
regulator-name = "vcc18_io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_io";
regulator-boot-on;
};
vdd10_video: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd10_video";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_video";
regulator-always-on;
regulator-boot-on;
};
vcc18_video: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc18_video";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_video";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&uart0 {
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&pinctrl {
leds {
module_led_pins: module-led-pins {
rockchip,pins =
<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
pmic_sleep: pmic-sleep {
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
};
&spi1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spiflash: w25q32dw@0 {
norflash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <49500000>;
spi-cpol;
spi-cpha;
spi-max-frequency = <50000000>;
};
};
&uart1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&wdt {
status = "okay";
};

3
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
View file

@ -2,6 +2,9 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include "rk3368-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &emmc;

2
arch/arm/dts/rk3368-sheep-u-boot.dtsi
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@ -3,6 +3,8 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include "rk3368-u-boot.dtsi"
&pinctrl {
u-boot,dm-pre-reloc;
};

27
arch/arm/dts/rk3368-u-boot.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
#include <dt-bindings/memory/rk3368-dmc.h>
/ {
dmc: dmc@ff610000 {
compatible = "rockchip,rk3368-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
reg = <0 0xff610000 0 0x400
0 0xff620000 0 0x400>;
};
service_msch: syscon@ffac0000 {
compatible = "rockchip,rk3368-msch", "syscon";
reg = <0x0 0xffac0000 0x0 0x2000>;
};
sgrf: syscon@ff740000 {
compatible = "rockchip,rk3368-sgrf", "syscon";
reg = <0x0 0xff740000 0x0 0x1000>;
};
};

578
arch/arm/dts/rk3368.dtsi
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File diff suppressed because it is too large Load diff

7
arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 Alexandre Vicenzi <linux@alxd.me>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

52
arch/arm/dts/rk3399-nanopi-m4b.dts Normal file
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@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPi M4B board device tree source
*
* Copyright (c) 2020 Chen-Yu Tsai <wens@csie.org>
*/
/dts-v1/;
#include "rk3399-nanopi-m4.dts"
/ {
model = "FriendlyElec NanoPi M4B";
compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1500000>;
poll-interval = <100>;
recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
};
/* No USB type-C PD power manager */
/delete-node/ &fusb0;
&i2c4 {
status = "disabled";
};
&u2phy0_host {
phy-supply = <&vcc5v0_usb2>;
};
&u2phy0_otg {
phy-supply = <&vbus_typec>;
};
&u2phy1_otg {
phy-supply = <&vcc5v0_usb1>;
};
&vbus_typec {
enable-active-high;
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
};

16
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* RK3399-based FriendlyElec boards device tree source
*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
* Copyright (C) 2020 Xiaobo <peterwillcn@gmail.com>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"

138
arch/arm/dts/rk3399-nanopi-r4s.dts Normal file
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@ -0,0 +1,138 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
* Copyright (C) 2020 Xiaobo <peterwillcn@gmail.com>
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPi R4S";
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
aliases {
ethernet1 = &r8169;
};
vdd_5v: vdd-5v {
compatible = "regulator-fixed";
regulator-name = "vdd_5v";
regulator-always-on;
regulator-boot-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 12 18 255>;
#cooling-cells = <2>;
fan-supply = <&vdd_5v>;
pwms = <&pwm1 0 50000 0>;
};
};
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&emmc_phy {
status = "disabled";
};
&fusb0 {
status = "disabled";
};
&leds {
lan_led: led-1 {
gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
label = "nanopi-r4s:green:lan";
};
wan_led: led-2 {
gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
label = "nanopi-r4s:green:wan";
};
};
&leds_gpio {
rockchip,pins =
<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
&pcie0 {
max-link-speed = <1>;
num-lanes = <1>;
vpcie3v3-supply = <&vcc3v3_sys>;
pcie@0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8169: pcie@0,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&sdhci {
status = "disabled";
};
&sdio0 {
status = "disabled";
};
&sdmmc {
host-index-min = <1>;
};
&u2phy0_host {
phy-supply = <&vdd_5v>;
};
&u2phy1_host {
status = "disabled";
};
&usbdrd_dwc3_0 {
dr_mode = "host";
};
&vcc3v3_sys {
vin-supply = <&vcc5v0_sys>;
};

12
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
View file

@ -48,6 +48,18 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
};
&gpio1 {

5
arch/arm/mach-rockchip/rk3368/Kconfig
View file

@ -49,7 +49,7 @@ config SYS_SOC
default "rk3368"
config SYS_MALLOC_F_LEN
default 0x2000
default 0x4000
config SPL_LIBCOMMON_SUPPORT
default y
@ -65,6 +65,9 @@ source "board/rockchip/evb_px5/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds"
config SPL_STACK_R_ADDR
default 0x04000000
config TPL_MAX_SIZE
default 28672

12
board/rockchip/evb_rk3399/MAINTAINERS
View file

@ -49,12 +49,24 @@ S: Maintained
F: configs/nanopi-m4-2gb-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
NANOPI-M4B
M: Alexandre Vicenzi <linux@alxd.me>
S: Maintained
F: configs/nanopi-m4b-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi
NANOPI-NEO4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopi-neo4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
NANOPI-R4S
M: Xiaobo Tian <peterwillcn@gmail.com>
S: Maintained
F: configs/nanopi-r4s-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
ORANGEPI-RK3399
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

2
board/theobroma-systems/puma_rk3399/Kconfig
View file

@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
config ENV_SIZE
default 0x2000
default 0x4000
config ENV_OFFSET
default 0x3fc000 if ENV_IS_IN_SPI_FLASH

19
configs/lion-rk3368_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_LION_RK3368=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
@ -33,18 +33,22 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
@ -61,14 +65,15 @@ CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_TPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_MSCC=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
@ -77,6 +82,7 @@ CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
@ -87,6 +93,13 @@ CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y

61
configs/nanopi-m4b-rk3399_defconfig Normal file
View file

@ -0,0 +1,61 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b"
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

62
configs/nanopi-r4s-rk3399_defconfig Normal file
View file

@ -0,0 +1,62 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

4
configs/odroid-go2_defconfig
View file

@ -24,7 +24,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rk3326-odroidgo2.dtb"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -33,7 +33,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
@ -110,4 +109,3 @@ CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

1
configs/rock960-rk3399_defconfig
View file

@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SF is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y

1
doc/board/rockchip/rockchip.rst
View file

@ -61,6 +61,7 @@ List of mainline supported rockchip boards:
- Firefly ROC-RK3399-PC
- FriendlyElec NanoPC-T4 (nanopc-t4-rk3399)
- FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
- FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
- FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
- Google Bob (chromebook_bob)
- Khadas Edge (khadas-edge-rk3399)

4
include/configs/rk3368_common.h
View file

@ -24,13 +24,15 @@
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
#define CONFIG_SPL_STACK 0x00188000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \

2
include/configs/rk3399_common.h
View file

@ -75,6 +75,4 @@
#endif
/* enable usb config for usb ether */
#endif

31
include/dt-bindings/clock/rk3368-cru.h
View file

@ -1,15 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
@ -44,13 +35,12 @@
#define SCLK_I2S_8CH 82
#define SCLK_SPDIF_8CH 83
#define SCLK_I2S_2CH 84
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_TIMER4 89
#define SCLK_TIMER5 90
#define SCLK_TIMER6 91
#define SCLK_TIMER00 85
#define SCLK_TIMER01 86
#define SCLK_TIMER02 87
#define SCLK_TIMER03 88
#define SCLK_TIMER04 89
#define SCLK_TIMER05 90
#define SCLK_OTGPHY0 93
#define SCLK_OTG_ADP 96
#define SCLK_HSICPHY480M 97
@ -82,6 +72,12 @@
#define SCLK_SFC 126
#define SCLK_MAC 127
#define SCLK_MACREF_OUT 128
#define SCLK_TIMER10 133
#define SCLK_TIMER11 134
#define SCLK_TIMER12 135
#define SCLK_TIMER13 136
#define SCLK_TIMER14 137
#define SCLK_TIMER15 138
#define DCLK_VOP 190
#define MCLK_CRYPTO 191
@ -151,6 +147,7 @@
#define PCLK_ISP 366
#define PCLK_VIP 367
#define PCLK_WDT 368
#define PCLK_EFUSE256 369
/* hclk gates */
#define HCLK_SFC 448