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https://github.com/AsahiLinux/u-boot
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x86: apl: Add hex offsets for registers in FSP-S
When comparing hex dumps it is useful to see the offsets of the registers. Add them in where they correspond to a multiple of 16. Possibly it would be useful to have a a command to output the FSP values in human-readable form, making use of the fsp_bindings implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
501ba58ae6
commit
4711c1f548
1 changed files with 72 additions and 0 deletions
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@ -9,7 +9,15 @@
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#ifndef __ASSEMBLY__
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#include <asm/fsp2/fsp_api.h>
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/**
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* struct fsp_s_config - FSP-S configuration
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*
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* Note that struct fsp_upd_header preceeds this and is 32 bytes long. The
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* hex offsets mentioned in this file are relative to the start of the header,
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* the same convention used in Intel's APL FSP header file.
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*/
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struct __packed fsp_s_config {
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/* 0x20 */
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u8 active_processor_cores;
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u8 disable_core1;
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u8 disable_core2;
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@ -26,6 +34,8 @@ struct __packed fsp_s_config {
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u8 c_state_auto_demotion;
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u8 c_state_un_demotion;
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u8 max_core_c_state;
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/* 0x30 */
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u8 pkg_c_state_demotion;
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u8 pkg_c_state_un_demotion;
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u8 turbo_mode;
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@ -36,6 +46,8 @@ struct __packed fsp_s_config {
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u8 ipu_acpi_mode;
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u8 force_wake;
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u32 gtt_mm_adr;
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/* 0x40 */
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u32 gm_adr;
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u8 pavp_lock;
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u8 graphics_freq_modify;
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@ -49,6 +61,8 @@ struct __packed fsp_s_config {
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u8 power_gating;
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u8 unit_level_clock_gating;
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u8 fast_boot;
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/* 0x50 */
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u8 dyn_sr;
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u8 sa_ipu_enable;
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u8 pm_support;
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@ -56,6 +70,8 @@ struct __packed fsp_s_config {
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u32 logo_size;
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u32 logo_ptr;
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u32 graphics_config_ptr;
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/* 0x60 */
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u8 pavp_enable;
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u8 pavp_pr3;
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u8 cd_clock;
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@ -78,6 +94,8 @@ struct __packed fsp_s_config {
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u8 hda_enable;
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u8 dsp_enable;
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u8 pme;
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/* 0x90 */
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u8 hd_audio_io_buffer_ownership;
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u8 hd_audio_io_buffer_voltage;
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u8 hd_audio_vc_type;
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@ -94,6 +112,8 @@ struct __packed fsp_s_config {
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u8 hmt;
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u8 hd_audio_pwr_gate;
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u8 hd_audio_clk_gate;
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/* 0xa0 */
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u32 dsp_feature_mask;
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u32 dsp_pp_module_mask;
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u8 bios_cfg_lock_down;
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@ -104,6 +124,8 @@ struct __packed fsp_s_config {
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u8 hpet_function_number;
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u8 io_apic_bdf_valid;
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u8 io_apic_bus_number;
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/* 0xb0 */
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u8 io_apic_device_number;
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u8 io_apic_function_number;
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u8 io_apic_entry24_119;
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@ -124,6 +146,8 @@ struct __packed fsp_s_config {
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u8 i2c2_enable;
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u8 i2c3_enable;
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u8 i2c4_enable;
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/* 0xd0 */
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u8 i2c5_enable;
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u8 i2c6_enable;
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u8 i2c7_enable;
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@ -137,6 +161,8 @@ struct __packed fsp_s_config {
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u8 os_dbg_enable;
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u8 dci_en;
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u32 uart2_kernel_debug_base_address;
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/* 0xe0 */
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u8 pcie_clock_gating_disabled;
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u8 pcie_root_port8xh_decode;
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u8 pcie8xh_decode_port_index;
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@ -150,6 +176,8 @@ struct __packed fsp_s_config {
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u8 pcie_rp_pm_sci[6];
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u8 pcie_rp_ext_sync[6];
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u8 pcie_rp_transmitter_half_swing[6];
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/* 0x110 */
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u8 pcie_rp_acs_enabled[6];
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u8 pcie_rp_clk_req_supported[6];
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u8 pcie_rp_clk_req_number[6];
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@ -158,6 +186,8 @@ struct __packed fsp_s_config {
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u8 pme_interrupt[6];
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u8 unsupported_request_report[6];
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u8 fatal_error_report[6];
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/* 0x140 */
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u8 no_fatal_error_report[6];
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u8 correctable_error_report[6];
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u8 system_error_on_fatal_error[6];
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@ -166,6 +196,8 @@ struct __packed fsp_s_config {
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u8 pcie_rp_speed[6];
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u8 physical_slot_number[6];
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u8 pcie_rp_completion_timeout[6];
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/* 0x170 */
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u8 ptm_enable[6];
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u8 pcie_rp_aspm[6];
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u8 pcie_rp_l1_substates[6];
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@ -173,6 +205,8 @@ struct __packed fsp_s_config {
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u8 pcie_rp_ltr_config_lock[6];
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u8 pme_b0_s5_dis;
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u8 pci_clock_run;
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/* 0x190 */
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u8 timer8254_clk_setting;
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u8 enable_sata;
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u8 sata_mode;
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@ -185,6 +219,8 @@ struct __packed fsp_s_config {
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u8 sata_ports_dev_slp[2];
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u8 sata_ports_hot_plug[2];
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u8 sata_ports_interlock_sw[2];
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/* 0x1a0 */
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u8 sata_ports_external[2];
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u8 sata_ports_spin_up[2];
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u8 sata_ports_solid_state_drive[2];
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@ -192,6 +228,8 @@ struct __packed fsp_s_config {
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u8 sata_ports_dm_val[2];
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u8 unused_upd_space3[2];
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u16 sata_ports_dito_val[2];
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/* 0x1b0 */
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u16 sub_system_vendor_id;
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u16 sub_system_id;
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u8 crid_settings;
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@ -206,6 +244,8 @@ struct __packed fsp_s_config {
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u8 sirq_mode;
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u8 start_frame_pulse;
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u8 smbus_enable;
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/* 0x1c0 */
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u8 arp_enable;
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u8 unused_upd_space4;
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u16 num_rsvd_smbus_addresses;
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@ -215,10 +255,14 @@ struct __packed fsp_s_config {
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u8 usb30_mode;
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u8 unused_upd_space5[1];
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u8 port_usb20_enable[8];
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/* 0x250 */
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u8 port_us20b_over_current_pin[8];
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u8 usb_otg;
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u8 hsic_support_enable;
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u8 port_usb30_enable[6];
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/* 0x260 */
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u8 port_us30b_over_current_pin[6];
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u8 ssic_port_enable[2];
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u16 dlane_pwr_gating;
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@ -227,9 +271,13 @@ struct __packed fsp_s_config {
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u16 reset_wait_timer;
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u8 rtc_lock;
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u8 sata_test_mode;
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/* 0x270 */
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u8 ssic_rate[2];
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u16 dynamic_power_gating;
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u16 pcie_rp_ltr_max_snoop_latency[6];
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/* 0x280 */
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u8 pcie_rp_snoop_latency_override_mode[6];
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u8 unused_upd_space6[2];
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u16 pcie_rp_snoop_latency_override_value[6];
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@ -240,45 +288,69 @@ struct __packed fsp_s_config {
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u8 pcie_rp_non_snoop_latency_override_mode[6];
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u8 tco_timer_halt_lock;
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u8 pwr_btn_override_period;
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/* 0x2b0 */
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u16 pcie_rp_non_snoop_latency_override_value[6];
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u8 pcie_rp_non_snoop_latency_override_multiplier[6];
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u8 pcie_rp_slot_power_limit_scale[6];
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u8 pcie_rp_slot_power_limit_value[6];
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u8 disable_native_power_button;
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u8 power_butter_debounce_mode;
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/* 0x2d0 */
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u32 sdio_tx_cmd_cntl;
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u32 sdio_tx_data_cntl1;
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u32 sdio_tx_data_cntl2;
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u32 sdio_rx_cmd_data_cntl1;
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/* 0x2e0 */
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u32 sdio_rx_cmd_data_cntl2;
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u32 sdcard_tx_cmd_cntl;
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u32 sdcard_tx_data_cntl1;
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u32 sdcard_tx_data_cntl2;
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/* 0x2f0 */
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u32 sdcard_rx_cmd_data_cntl1;
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u32 sdcard_rx_strobe_cntl;
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u32 sdcard_rx_cmd_data_cntl2;
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u32 emmc_tx_cmd_cntl;
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/* 0x300 */
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u32 emmc_tx_data_cntl1;
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u32 emmc_tx_data_cntl2;
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u32 emmc_rx_cmd_data_cntl1;
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u32 emmc_rx_strobe_cntl;
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/* 0x310 */
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u32 emmc_rx_cmd_data_cntl2;
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u32 emmc_master_sw_cntl;
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u8 pcie_rp_selectable_deemphasis[6];
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u8 monitor_mwait_enable;
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u8 hd_audio_dsp_uaa_compliance;
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/* 0x320 */
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u32 ipc[4];
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/* 0x330 */
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u8 sata_ports_disable_dynamic_pg[2];
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u8 init_s3_cpu;
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u8 skip_punit_init;
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u8 unused_upd_space7[4];
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u8 port_usb20_per_port_tx_pe_half[8];
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/* 0x340 */
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u8 port_usb20_per_port_pe_txi_set[8];
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u8 port_usb20_per_port_txi_set[8];
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/* 0x350 */
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u8 port_usb20_hs_skew_sel[8];
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u8 port_usb20_i_usb_tx_emphasis_en[8];
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/* 0x360 */
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u8 port_usb20_per_port_rxi_set[8];
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u8 port_usb20_hs_npre_drv_sel[8];
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/* 0x370 */
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u8 reserved_fsps_upd[16];
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};
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