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arm: am57xx: cl-som-am57x: add initial board support

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Features supported :

* Serial console
* SPI Flash
* MMC/SD Card
* eMMC storage
* SATA
* PCA9555 - GPIO expander over I2C5 bus
* USB

Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
[uri.mashiach@compulab.co.il: Adjust to v2016.11]
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This commit is contained in:
Dmitry Lifshitz 2016-12-28 18:28:33 +02:00 committed by Tom Rini
parent 6d799d04a8
commit 46650d583b
9 changed files with 579 additions and 0 deletions
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4
arch/arm/mach-omap2/omap5/Kconfig
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@ -40,6 +40,9 @@ choice
prompt "OMAP5 board select"
optional
config TARGET_CL_SOM_AM57X
bool "CompuLab CL-SOM-AM57x"
config TARGET_CM_T54
bool "CompuLab CM-T54"
@ -179,6 +182,7 @@ endchoice
endmenu
endif
source "board/compulab/cl-som-am57x/Kconfig"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"

12
board/compulab/cl-som-am57x/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_CL_SOM_AM57X
config SYS_BOARD
default "cl-som-am57x"
config SYS_VENDOR
default "compulab"
config SYS_CONFIG_NAME
default "cl-som-am57x"
endif

6
board/compulab/cl-som-am57x/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
CL-SOM-AM57x BOARD
M: Uri Mashiach <uri.mashiach@compulab.co.il>
S: Maintained
F: board/compulab/cl-som-am57x/
F: include/configs/cl-som-am57x.h
F: configs/cl-som-am57x_defconfig

15
board/compulab/cl-som-am57x/Makefile Normal file
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@ -0,0 +1,15 @@
#
# Makefile
#
# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il>
#
# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o mux.o
else
obj-y += cl-som-am57x.o mux.o
endif

62
board/compulab/cl-som-am57x/cl-som-am57x.c Normal file
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@ -0,0 +1,62 @@
/*
* Board functions for CompuLab cl_som_am57x board
*
* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <usb.h>
#include <asm/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: CL-SOM-AM57x\n"
};
int board_init(void)
{
/* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_GENERIC_MMC
#define SB_SOM_CD_GPIO 187
#define SB_SOM_WP_GPIO 188
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
if (ret0)
printf("cl-som-am57x: failed to initialize mmc0\n");
ret1 = omap_mmc_init(1, 0, 0, -1, -1);
if (ret1)
printf("cl-som-am57x: failed to initialize mmc1\n");
return ret0 && ret1;
}
#endif /* CONFIG_GENERIC_MMC */
#ifdef CONFIG_USB_XHCI_OMAP
int board_usb_init(int index, enum usb_init_type init)
{
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
return 0;
}
#endif /* CONFIG_USB_XHCI_OMAP */

100
board/compulab/cl-som-am57x/mux.c Normal file
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@ -0,0 +1,100 @@
/*
* Pinmux configuration for CompuLab CL-SOM-AM57x board
*
* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux_dra7xx.h>
/* Serial console */
static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
{UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */
{UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */
};
/* PMIC I2C */
static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
{MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */
{MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */
};
/* Green GPIO led */
static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
{GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */
};
/* MMC/SD Card */
static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
{MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */
{MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */
{MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */
{MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */
{MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */
{MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */
{MMC1_SDCD, (IEN | PEN | M14)}, /* MMC1_SDCD */
{MMC1_SDWP, (IEN | PEN | M14)}, /* MMC1_SDWP */
};
/* WiFi - must be in the safe mode on boot */
static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
{UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */
{UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */
{UART2_RXD, (IEN | M15)}, /* UART2_RXD */
{UART2_TXD, (IEN | M15)}, /* UART2_TXD */
{UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */
{UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */
};
/* QSPI */
static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
{GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */
{GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */
{GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */
{GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */
{GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */
};
/* GPIO Expander I2C */
static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
{MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */
{MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */
};
/* eMMC internal storage */
static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
{GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */
{GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */
{GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */
{GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */
{GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */
{GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */
{GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */
{GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */
{GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */
{GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */
};
/* usb1_drvvbus */
static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
{USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */
};
#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
mux_array, ARRAY_SIZE(mux_array))
void set_muxconf_regs(void)
{
SET_MUX(cl_som_am57x_padconf_console);
SET_MUX(cl_som_am57x_padconf_pmic);
SET_MUX(cl_som_am57x_padconf_green_led);
SET_MUX(cl_som_am57x_padconf_sd_card);
SET_MUX(cl_som_am57x_padconf_wifi);
SET_MUX(cl_som_am57x_padconf_qspi);
SET_MUX(cl_som_am57x_padconf_i2c_gpio);
SET_MUX(cl_som_am57x_padconf_emmc);
SET_MUX(cl_som_am57x_padconf_usb);
}

234
board/compulab/cl-som-am57x/spl.c Normal file
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@ -0,0 +1,234 @@
/*
* SPL data and initialization for CompuLab CL-SOM-AM57x board
*
* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
*
* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <asm/arch/sys_proto.h>
static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
*dmm_lisa_regs = &cl_som_am57x_lisa_regs;
}
static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61852332,
.sdram_config = 0x61852332,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040f1,
.ref_ctrl_final = 0x00001040,
.sdram_tim1 = 0xeeef36f3,
.sdram_tim2 = 0x348f7fda,
.sdram_tim3 = 0x027f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0034400b,
.emif_ddr_phy_ctlr_1 = 0x0e34400b,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
0x10040100,
0x00740074,
0x00780078,
0x007c007c,
0x007b007b,
0x00800080,
0x00360036,
0x00340034,
0x00360036,
0x00350035,
0x00350035,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x00430043,
0x003e003e,
0x004a004a,
0x00470047,
0x00400040,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0
};
static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61852332,
.sdram_config = 0x61852332,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040f1,
.ref_ctrl_final = 0x00001040,
.sdram_tim1 = 0xeeef36f3,
.sdram_tim2 = 0x348f7fda,
.sdram_tim3 = 0x027f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0034400b,
.emif_ddr_phy_ctlr_1 = 0x0e34400b,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
0x10040100,
0x00820082,
0x008b008b,
0x00800080,
0x007e007e,
0x00800080,
0x00370037,
0x00390039,
0x00360036,
0x00370037,
0x00350035,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x00540054,
0x00540054,
0x004e004e,
0x004c004c,
0x00400040,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0
};
static struct vcores_data cl_som_am57x_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*omap_vcores = &cl_som_am57x_volts;
*ctrl = &dra7xx_ctrl;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
*regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
break;
case 2:
*regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
break;
}
}
void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
switch (emif_nr) {
case 1:
*regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
*size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
break;
case 2:
*regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
*size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
break;
}
}

41
configs/cl-som-am57x_defconfig Normal file
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CONFIG_ARM=y
CONFIG_OMAP54XX=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_CL_SOM_AM57X=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y

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include/configs/cl-som-am57x.h Normal file
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/*
* Configuration settings for CompuLab CL-SOM-AM57x board
*
* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_CL_SOM_AM57X_H
#define __CONFIG_CL_SOM_AM57X_H
#define CONFIG_DRA7XX
#define CONFIG_NR_DRAM_BANKS 2
#define CONSOLEDEV "ttyO2"
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_OMAP_ABE_SYSCK
#include <configs/ti_omap5_common.h>
/* Status LED */
#define CONFIG_STATUS_LED /* Status LED enabled */
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define GREEN_LED_DEV 0
/* cl_som_am57x Green LED is GPIO2_5 */
#define GREEN_LED_GPIO 37
#define STATUS_LED_BIT GREEN_LED_GPIO
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
/* PMIC I2C bus number */
#define CONFIG_SYS_SPD_BUS_NUM 3
/* SPI Flash support */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
/* SPI SPL defines */
/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
/* SD/MMC RAW boot */
#undef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
#undef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
/* Environment */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#ifndef CONFIG_SPL_BUILD
/* SATA */
#define CONFIG_CMD_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* PCA9555 GPIO expander support */
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
/* GPT */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
/* USB Networking options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RNDIS
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#endif /* !CONFIG_SPL_BUILD */
#endif /* __CONFIG_CL_SOM_AM57X_H */