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https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
arm: mvebu: eDPU: support new board revision
There is a new eDPU revision that uses Marvell 88E6361 switch onboard. We can rely on detecting the switch to enable and fixup the Linux DTS so a single DTS can be used. There is currently no support for the 88E6361 switch and thus no working networking in U-Boot, so we disable both ports. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
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parent
fde58124c3
commit
46471e6c1d
4 changed files with 184 additions and 5 deletions
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@ -32,14 +32,17 @@
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bootph-all;
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};
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ð0 {
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/* G.hn does not work without additional configuration */
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status = "disabled";
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};
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ð1 {
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/*
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* eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
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* to patch the Linux DTS if its found so enable MDIO by default.
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*/
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&mdio {
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status = "okay";
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};
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@ -12,3 +12,50 @@
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ð0 {
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phy-mode = "2500base-x";
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};
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/*
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* External MV88E6361 switch is only available on v2 of the board.
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* U-Boot will enable the MDIO bus and switch nodes.
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*/
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&mdio {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&smi_pins>;
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/* Actual device is MV88E6361 */
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switch: switch@0 {
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compatible = "marvell,mv88e6190";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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ethernet = <ð0>;
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};
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port@9 {
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reg = <9>;
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label = "downlink";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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};
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port@a {
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reg = <10>;
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label = "uplink";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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sfp = <&sfp_eth1>;
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};
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};
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};
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};
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@ -14,6 +14,7 @@
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#include <mmc.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fdt_support.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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@ -50,6 +51,7 @@ DECLARE_GLOBAL_DATA_PTR;
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/* Single-chip mode */
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/* Switch Port Registers */
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#define MVEBU_SW_LINK_CTRL_REG (1)
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#define MVEBU_SW_PORT_SWITCH_ID (3)
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#define MVEBU_SW_PORT_CTRL_REG (4)
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#define MVEBU_SW_PORT_BASE_VLAN (6)
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@ -57,6 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MVEBU_G2_SMI_PHY_CMD_REG (24)
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#define MVEBU_G2_SMI_PHY_DATA_REG (25)
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#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
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/*
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* Memory Controller Registers
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*
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@ -73,6 +77,30 @@ DECLARE_GLOBAL_DATA_PTR;
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#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
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#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
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static bool is_edpu_plus(void)
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{
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struct udevice *bus;
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ofnode node;
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int val;
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if (!CONFIG_IS_ENABLED(DM_MDIO))
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return false;
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node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
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if (!ofnode_valid(node) ||
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uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
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device_probe(bus)) {
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printf("Cannot find MDIO bus\n");
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return -ENODEV;
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}
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val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
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if (val == SWITCH_88E6361_PRODUCT_NUMBER)
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return true;
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else
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return false;
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}
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int board_early_init_f(void)
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{
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return 0;
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@ -357,6 +385,41 @@ static int espressobin_last_stage_init(void)
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return 0;
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}
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static int edpu_plus_last_stage_init(void)
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{
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struct udevice *dev;
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int ret;
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if (is_edpu_plus()) {
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ret = uclass_get_device_by_name(UCLASS_ETH,
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"ethernet@40000",
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&dev);
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if (!ret) {
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device_remove(dev, DM_REMOVE_NORMAL);
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device_unbind(dev);
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}
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/* Currently no networking support on the eDPU+ board */
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ret = uclass_get_device_by_name(UCLASS_ETH,
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"ethernet@30000",
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&dev);
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if (!ret) {
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device_remove(dev, DM_REMOVE_NORMAL);
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device_unbind(dev);
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}
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} else {
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ret = uclass_get_device_by_name(UCLASS_ETH,
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"ethernet@30000",
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&dev);
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if (!ret) {
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device_remove(dev, DM_REMOVE_NORMAL);
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device_unbind(dev);
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}
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}
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return 0;
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}
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/* Bring-up board-specific network stuff */
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static int last_stage_init(void)
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{
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@ -364,6 +427,9 @@ static int last_stage_init(void)
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if (of_machine_is_compatible("globalscale,espressobin"))
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return espressobin_last_stage_init();
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if (of_machine_is_compatible("methode,edpu"))
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return edpu_plus_last_stage_init();
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return 0;
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}
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EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
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@ -465,12 +531,74 @@ static int espressobin_fdt_setup(void *blob)
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return 0;
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}
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static int edpu_plus_fdt_setup(void *blob)
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{
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const char *ports[] = { "downlink", "uplink" };
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uint8_t mac[ETH_ALEN];
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const char *path;
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int i, ret;
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if (is_edpu_plus()) {
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ret = fdt_set_status_by_compatible(blob,
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"marvell,orion-mdio",
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FDT_STATUS_OKAY);
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if (ret)
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printf("Failed to enable MDIO!\n");
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ret = fdt_set_status_by_alias(blob,
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"ethernet1",
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FDT_STATUS_DISABLED);
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if (ret)
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printf("Failed to disable ethernet1!\n");
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path = fdt_get_alias(blob, "ethernet0");
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if (path)
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do_fixup_by_path_string(blob, path, "phy-mode", "2500base-x");
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else
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printf("Failed to update ethernet0 phy-mode to 2500base-x!\n");
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ret = fdt_set_status_by_compatible(blob,
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"marvell,mv88e6190",
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FDT_STATUS_OKAY);
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if (ret)
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printf("Failed to enable MV88E6361!\n");
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/*
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* MAC-s for Uplink and Downlink ports are stored under
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* non standard variable names, so lets manually fixup the
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* switch port nodes to have the desired MAC-s.
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*/
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for (i = 0; i < 2; i++) {
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if (eth_env_get_enetaddr(ports[i], mac)) {
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do_fixup_by_prop(blob,
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"label",
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ports[i],
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strlen(ports[i]) + 1,
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"mac-address",
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mac, ARP_HLEN, 1);
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do_fixup_by_prop(blob,
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"label",
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ports[i],
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strlen(ports[i]) + 1,
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"local-mac-address",
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mac, ARP_HLEN, 1);
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}
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}
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}
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
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if (of_machine_is_compatible("globalscale,espressobin"))
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return espressobin_fdt_setup(blob);
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#endif
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if (of_machine_is_compatible("methode,edpu"))
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return edpu_plus_fdt_setup(blob);
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return 0;
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}
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#endif
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@ -17,6 +17,7 @@ CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_USE_PREBOOT=y
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CONFIG_SYS_PBSIZE=1048
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# CONFIG_DISPLAY_CPUINFO is not set
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