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MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE

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Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT
(or CONF_CM_CACHABLE_COW when a CM is available). There is no
need to make this configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Daniel Schwierzeck 2018-09-07 19:02:06 +02:00
parent 5ef337a037
commit 46203baf66
5 changed files with 1 additions and 26 deletions
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14
README
View file

@ -528,20 +528,6 @@ The following options need to be configured:
pointer. This is needed for the temporary stack before pointer. This is needed for the temporary stack before
relocation. relocation.
CONFIG_SYS_MIPS_CACHE_MODE
Cache operation mode for the MIPS CPU.
See also arch/mips/include/asm/mipsregs.h.
Possible values are:
CONF_CM_CACHABLE_NO_WA
CONF_CM_CACHABLE_WA
CONF_CM_UNCACHED
CONF_CM_CACHABLE_NONCOHERENT
CONF_CM_CACHABLE_CE
CONF_CM_CACHABLE_COW
CONF_CM_CACHABLE_CUW
CONF_CM_CACHABLE_ACCELERATED
CONFIG_XWAY_SWAP_BYTES CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq Enable compilation of tools/xway-swap-bytes needed for Lantiq

6
arch/mips/lib/cache_init.S
View file

@ -14,10 +14,6 @@
#include <asm/cacheops.h> #include <asm/cacheops.h>
#include <asm/cm.h> #include <asm/cm.h>
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
.macro f_fill64 dst, offset, val .macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
@ -331,7 +327,7 @@ l1_init:
and t0, t0, t1 and t0, t0, t1
PTR_LI t1, CKSEG1 PTR_LI t1, CKSEG1
or t0, t0, t1 or t0, t0, t1
li a0, CONFIG_SYS_MIPS_CACHE_MODE li a0, CONF_CM_CACHABLE_NONCOHERENT
jalr.hb t0 jalr.hb t0
/* /*

3
include/configs/imgtec_xilfpga.h
View file

@ -19,9 +19,6 @@
/* CPU Timer rate */ /* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 #define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
/* Cache Configuration */
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
* Memory Layout * Memory Layout
*/ */

3
include/configs/pic32mzdask.h
View file

@ -16,9 +16,6 @@
/* CPU Timer rate */ /* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 #define CONFIG_SYS_MIPS_TIMER_FREQ 100000000
/* Cache Configuration */
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
* Memory Layout * Memory Layout
*/ */

1
scripts/config_whitelist.txt
View file

@ -3424,7 +3424,6 @@ CONFIG_SYS_MEM_TOP_HIDE
CONFIG_SYS_MFD CONFIG_SYS_MFD
CONFIG_SYS_MHZ CONFIG_SYS_MHZ
CONFIG_SYS_MII_MODE CONFIG_SYS_MII_MODE
CONFIG_SYS_MIPS_CACHE_MODE
CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR