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Merge with git://www.denx.de/git/u-boot.git

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This commit is contained in:
Stefan Roese 2007-07-06 14:49:28 +02:00
commit 461f2274f8
32 changed files with 2061 additions and 313 deletions
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2
Makefile
View file

@ -214,6 +214,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \

9
board/amcc/sequoia/sequoia.c
View file

@ -25,7 +25,6 @@
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
#include "sequoia.h"
DECLARE_GLOBAL_DATA_PTR;
@ -226,7 +225,7 @@ int misc_init_r(void)
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
@ -254,7 +253,7 @@ int misc_init_r(void)
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
@ -298,7 +297,7 @@ int misc_init_r(void)
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@ -323,7 +322,7 @@ int misc_init_r(void)
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets*/

67
board/amcc/sequoia/sequoia.h
View file

@ -1,67 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*----------------------------------------------------------------------------+
| EBC Configuration Register - EBC0_CFG
+----------------------------------------------------------------------------*/
/* External Bus Three-State Control */
#define EBC0_CFG_EBTC_DRIVEN 0x80000000
/* Device-Paced Time-out Disable */
#define EBC0_CFG_PTD_ENABLED 0x00000000
/* Ready Timeout Count */
#define EBC0_CFG_RTC_MASK 0x38000000
#define EBC0_CFG_RTC_16PERCLK 0x00000000
#define EBC0_CFG_RTC_32PERCLK 0x08000000
#define EBC0_CFG_RTC_64PERCLK 0x10000000
#define EBC0_CFG_RTC_128PERCLK 0x18000000
#define EBC0_CFG_RTC_256PERCLK 0x20000000
#define EBC0_CFG_RTC_512PERCLK 0x28000000
#define EBC0_CFG_RTC_1024PERCLK 0x30000000
#define EBC0_CFG_RTC_2048PERCLK 0x38000000
/* External Master Priority Low */
#define EBC0_CFG_EMPL_LOW 0x00000000
#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
#define EBC0_CFG_EMPL_HIGH 0x06000000
/* External Master Priority High */
#define EBC0_CFG_EMPH_LOW 0x00000000
#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
#define EBC0_CFG_EMPH_HIGH 0x01800000
/* Chip Select Three-State Control */
#define EBC0_CFG_CSTC_DRIVEN 0x00400000
/* Burst Prefetch */
#define EBC0_CFG_BPF_ONEDW 0x00000000
#define EBC0_CFG_BPF_TWODW 0x00100000
#define EBC0_CFG_BPF_FOURDW 0x00200000
/* External Master Size */
#define EBC0_CFG_EMS_8BIT 0x00000000
/* Power Management Enable */
#define EBC0_CFG_PME_DISABLED 0x00000000
#define EBC0_CFG_PME_ENABLED 0x00020000
/* Power Management Timer */
#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
#define SDR0_USB0 0x0320 /* USB Control Register */

17
board/lwmon5/lwmon5.c
View file

@ -19,9 +19,10 @@
*/
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -220,6 +221,13 @@ int misc_init_r(void)
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
/* Lime memory clock adjusted to 133MHz */
out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
* Reset PHY's
*/
@ -229,13 +237,6 @@ int misc_init_r(void)
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
/*
* Reset USB hub
*/
gpio_write_bit(CFG_GPIO_HUB_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_HUB_RST, 1);
return 0;
}

64
board/lwmon5/sdram.c
View file

@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
* Therefore we don't fill the memory with a pattern or
* just zero it, but write the same values back that are
* already in the memory cells.
*/
address_increment = CFG_CACHELINE_SIZE;
end_address = current_address + num_bytes;
current_address = start_address;
while (current_address < end_address) {
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
}
#else
dcbz_area(start_address, num_bytes);
dflush();
#endif
}
sync();
@ -518,6 +537,8 @@ long int initdram (int board_type)
{
u32 val;
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
@ -558,6 +579,49 @@ long int initdram (int board_type)
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#else
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
mtsdram(DDR0_04, 0x0B030300);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0003C812);
mtsdram(DDR0_07, 0x00090100);
mtsdram(DDR0_08, 0x03c80001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x000CC800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x1e000000);
mtsdram(DDR0_18, 0x1e1e1e1e);
mtsdram(DDR0_19, 0x1e1e1e1e);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
#ifdef CONFIG_DDR_ECC
mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
#else
mtsdram(DDR0_22, 0x00267F0B);
#endif
mtsdram(DDR0_23, 0x01000000);
mtsdram(DDR0_24, 0x01010001);
mtsdram(DDR0_26, 0x2D93028A);
mtsdram(DDR0_27, 0x0784682B);
mtsdram(DDR0_28, 0x00000080);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000008);
mtsdram(DDR0_43, 0x050A0200);
mtsdram(DDR0_44, 0x00000005);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#endif
wait_for_dlllock();

274
board/stxssa/stxssa.c
View file

@ -52,147 +52,147 @@ long int fixed_sdram (void);
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
@ -227,12 +227,12 @@ reset_phy(void)
#if (CONFIG_ETHER_INDEX == 2)
bcsr->bcsr2 &= ~FETH2_RST;
udelay(2);
bcsr->bcsr2 |= FETH2_RST;
bcsr->bcsr2 |= FETH2_RST;
udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
bcsr->bcsr3 &= ~FETH3_RST;
udelay(2);
bcsr->bcsr3 |= FETH3_RST;
bcsr->bcsr3 |= FETH3_RST;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
@ -252,10 +252,10 @@ int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xfffffffdf; /* disable master abort */
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
/* Why is the phy reset done _after_ the ethernet

8
cpu/ppc4xx/start.S
View file

@ -1217,15 +1217,23 @@ mck_return:
* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
* although for some cache-ralated calls stubs have to be provided to satisfy
* symbols resolution.
* Icache-related functions are used in POST framework.
*
*/
#ifdef CONFIG_440
.globl dcache_disable
.globl icache_disable
.globl icache_enable
dcache_disable:
icache_disable:
icache_enable:
blr
.globl dcache_status
.globl icache_status
dcache_status:
icache_status:
mr r3, 0
blr
#else
flush_dcache:

16
include/configs/lwmon5.h
View file

@ -326,13 +326,25 @@
#define CFG_EBC_CFG 0xb8400000
/*-----------------------------------------------------------------------
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
/* Lime Clock frequency is to set 133MHz */
#define CFG_LIME_CLOCK_133MHZ 0x10000
/* SDRAM Parameter register */
#define CFG_LIME_MMR 0xC1FCFFFC
/* SDRAM parameter value */
#define CFG_LIME_MMR_VALUE 0x414FB7F2
/*-----------------------------------------------------------------------
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_PHY1_RST 12
#define CFG_GPIO_FLASH_WP 14
#define CFG_GPIO_PHY0_RST 22
#define CFG_GPIO_HUB_RST 50
#define CFG_GPIO_WATCHDOG 58
#define CFG_GPIO_LIME_S 59
#define CFG_GPIO_LIME_RST 60
@ -396,7 +408,7 @@
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \

4
include/configs/sequoia.h
View file

@ -334,10 +334,14 @@
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_FPU | \
CFG_POST_ETHER | \
CFG_POST_SPR)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

126
include/configs/stxssa.h
View file

@ -42,20 +42,20 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/* sysclk for MPC85xx
*/
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
/* Blinkin' LEDs for Robert :-)
*/
@ -64,23 +64,23 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
/* Localbus connector. There are many options that can be
/* Localbus connector. There are many options that can be
* connected here, including sdram or lots of flash.
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
@ -88,16 +88,16 @@
* sizes.
*/
#ifdef CONFIG_STXSSA_4M
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
#else
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
#endif
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@ -110,22 +110,22 @@
*/
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#undef CFG_RAMBOOT
#endif
#ifdef CFG_RAMBOOT
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#else
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@ -140,14 +140,14 @@
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
@ -158,52 +158,52 @@
#define CFG_LBC_LSDMR_5 0x4061b723
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#if 0
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
#define CFG_I2C_OFFSET 0x3000
/* I2C EEPROM. AT24C32, we keep our environment in here.
/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
@ -232,26 +232,26 @@
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_EEPRO100
#define CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@ -260,7 +260,7 @@
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
@ -270,9 +270,9 @@
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
/*
@ -281,19 +281,19 @@
* - Select bus for bd/buffers
* - Full duplex
*/
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#if 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#else
#define CFG_FCC_PSMR 0
#define CFG_FCC_PSMR 0
#endif
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
@ -415,13 +415,13 @@
*/
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
#define CONFIG_BAUDRATE 38400
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP 192.168.85.1
#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_SSA
@ -431,7 +431,7 @@
#else /* ENV IS IN FLASH -- use a full-blown envionment */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */

8
include/ppc440.h
View file

@ -282,7 +282,6 @@
#define sdr_sdstp3 0x4003
#endif /* CONFIG_440GX */
#ifdef CONFIG_440
/*----------------------------------------------------------------------------+
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+----------------------------------------------------------------------------*/
@ -306,7 +305,6 @@
#define MMUCR_IULXE 0x00400000
#define MMUCR_STS 0x00100000
#define MMUCR_STID_MASK 0x000000FF
#endif /* CONFIG_440 */
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
@ -1025,7 +1023,7 @@
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR_USB2D0CR 0x0320
#define SDR0_USB2D0CR 0x0320
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
@ -1423,7 +1421,7 @@
#define uicvr uic0vr
#define uicvcr uic0vcr
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
/*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's.
+----------------------------------------------------------------------------*/
@ -1492,9 +1490,11 @@
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#define CPR0_PERD 0xE0
#if !defined(CONFIG_440EPX)
#define CPR0_PERD_PERDV0_MASK 0x03000000
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#endif
#define CPR0_MALD 0x100
#define CPR0_MALD_MALDV0_MASK 0x03000000

2
post/cpu/mpc8xx/Makefile
View file

@ -24,6 +24,6 @@
LIB = libpostmpc8xx.a
AOBJS = cache_8xx.o
COBJS = ether.o spr.o uart.o usb.o watchdog.o
COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o
include $(TOPDIR)/post/rules.mk

0
post/drivers/cache.c → post/cpu/mpc8xx/cache.c
View file

3
post/cpu/ppc4xx/Makefile
View file

@ -23,6 +23,7 @@
LIB = libpostppc4xx.a
COBJS = fpu.o spr.o uart.o watchdog.o
AOBJS = cache_4xx.o
COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o
include $(TOPDIR)/post/rules.mk

114
post/cpu/ppc4xx/cache.c Normal file
View file

@ -0,0 +1,114 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/* Cache test
*
* This test verifies the CPU data and instruction cache using
* several test scenarios.
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_CACHE
#include <asm/mmu.h>
#include <watchdog.h>
#define CACHE_POST_SIZE 1024
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
int cache_post_test1 (int tlb, void *p, int size);
int cache_post_test2 (int tlb, void *p, int size);
int cache_post_test3 (int tlb, void *p, int size);
int cache_post_test4 (int tlb, void *p, int size);
int cache_post_test5 (int tlb, void *p, int size);
int cache_post_test6 (int tlb, void *p, int size);
static int tlb = -1; /* index to the victim TLB entry */
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
int cache_post_test (int flags)
{
void* virt = (void*)CFG_POST_CACHE_ADDR;
int ints, i, res = 0;
u32 word0;
if (tlb < 0) {
/*
* Allocate a new TLB entry, since we are going to modify
* the write-through and caching inhibited storage attributes.
*/
program_tlb((u32)testarea, (u32)virt,
CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
/* Find the TLB entry */
for (i = 0;; i++) {
if (i >= PPC4XX_TLB_SIZE) {
printf ("Failed to program tlb entry\n");
return -1;
}
word0 = mftlb1(i);
if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
tlb = i;
break;
}
}
}
ints = disable_interrupts ();
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
WATCHDOG_RESET ();
if (res == 0)
res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
if (ints)
enable_interrupts ();
return res;
}
#endif /* CONFIG_POST & CFG_POST_CACHE */
#endif /* CONFIG_POST */

448
post/cpu/ppc4xx/cache_4xx.S Normal file
View file

@ -0,0 +1,448 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#ifdef CONFIG_POST
#include <post.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#if CONFIG_POST & CFG_POST_CACHE
.text
/* void cache_post_disable (int tlb)
*/
cache_post_disable:
tlbre r0, r3, 0x0002
ori r0, r0, TLB_WORD2_I_ENABLE@l
tlbwe r0, r3, 0x0002
sync
isync
blr
/* void cache_post_wt (int tlb)
*/
cache_post_wt:
tlbre r0, r3, 0x0002
ori r0, r0, TLB_WORD2_W_ENABLE@l
andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
tlbwe r0, r3, 0x0002
sync
isync
blr
/* void cache_post_wb (int tlb)
*/
cache_post_wb:
tlbre r0, r3, 0x0002
andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
tlbwe r0, r3, 0x0002
sync
isync
blr
/* void cache_post_dinvalidate (void *p, int size)
*/
cache_post_dinvalidate:
dcbi r0, r3
addi r3, r3, CFG_CACHELINE_SIZE
subic. r4, r4, CFG_CACHELINE_SIZE
bgt cache_post_dinvalidate
sync
blr
/* void cache_post_dstore (void *p, int size)
*/
cache_post_dstore:
dcbst r0, r3
addi r3, r3, CFG_CACHELINE_SIZE
subic. r4, r4, CFG_CACHELINE_SIZE
bgt cache_post_dstore
sync
blr
/* void cache_post_dtouch (void *p, int size)
*/
cache_post_dtouch:
dcbt r0, r3
addi r3, r3, CFG_CACHELINE_SIZE
subic. r4, r4, CFG_CACHELINE_SIZE
bgt cache_post_dtouch
sync
blr
/* void cache_post_iinvalidate (void)
*/
cache_post_iinvalidate:
iccci r0, r0
sync
blr
/* void cache_post_memset (void *p, int val, int size)
*/
cache_post_memset:
mtctr r5
1:
stb r4, 0(r3)
addi r3, r3, 1
bdnz 1b
blr
/* int cache_post_check (void *p, int size)
*/
cache_post_check:
mtctr r4
1:
lbz r0, 0(r3)
addi r3, r3, 1
cmpwi r0, 0xff
bne 2f
bdnz 1b
li r3, 0
blr
2:
li r3, -1
blr
#define CACHE_POST_DISABLE() \
mr r3, r10; \
bl cache_post_disable
#define CACHE_POST_WT() \
mr r3, r10; \
bl cache_post_wt
#define CACHE_POST_WB() \
mr r3, r10; \
bl cache_post_wb
#define CACHE_POST_DINVALIDATE() \
mr r3, r11; \
mr r4, r12; \
bl cache_post_dinvalidate
#define CACHE_POST_DFLUSH() \
mr r3, r11; \
mr r4, r12; \
bl cache_post_dflush
#define CACHE_POST_DSTORE() \
mr r3, r11; \
mr r4, r12; \
bl cache_post_dstore
#define CACHE_POST_DTOUCH() \
mr r3, r11; \
mr r4, r12; \
bl cache_post_dtouch
#define CACHE_POST_IINVALIDATE() \
bl cache_post_iinvalidate
#define CACHE_POST_MEMSET(val) \
mr r3, r11; \
li r4, val; \
mr r5, r12; \
bl cache_post_memset
#define CACHE_POST_CHECK() \
mr r3, r11; \
mr r4, r12; \
bl cache_post_check; \
mr r13, r3
/*
* Write and read 0xff pattern with caching enabled.
*/
.global cache_post_test1
cache_post_test1:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WB()
CACHE_POST_DINVALIDATE()
/* Write the negative pattern to the test area */
CACHE_POST_MEMSET(0xff)
/* Read the test area */
CACHE_POST_CHECK()
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
mr r3, r13
mtlr r9
blr
/*
* Write zeroes with caching enabled.
* Write 0xff pattern with caching disabled.
* Read 0xff pattern with caching enabled.
*/
.global cache_post_test2
cache_post_test2:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WB()
CACHE_POST_DINVALIDATE()
/* Write the zero pattern to the test area */
CACHE_POST_MEMSET(0)
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
/* Write the negative pattern to the test area */
CACHE_POST_MEMSET(0xff)
CACHE_POST_WB()
/* Read the test area */
CACHE_POST_CHECK()
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
mr r3, r13
mtlr r9
blr
/*
* Write-through mode test.
* Write zeroes, store the cache, write 0xff pattern.
* Invalidate the cache.
* Check that 0xff pattern is read.
*/
.global cache_post_test3
cache_post_test3:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WT()
CACHE_POST_DINVALIDATE()
/* Cache the test area */
CACHE_POST_DTOUCH()
/* Write the zero pattern to the test area */
CACHE_POST_MEMSET(0)
CACHE_POST_DSTORE()
/* Write the negative pattern to the test area */
CACHE_POST_MEMSET(0xff)
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
/* Read the test area */
CACHE_POST_CHECK()
mr r3, r13
mtlr r9
blr
/*
* Write-back mode test.
* Write 0xff pattern, store the cache, write zeroes.
* Invalidate the cache.
* Check that 0xff pattern is read.
*/
.global cache_post_test4
cache_post_test4:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WB()
CACHE_POST_DINVALIDATE()
/* Cache the test area */
CACHE_POST_DTOUCH()
/* Write the negative pattern to the test area */
CACHE_POST_MEMSET(0xff)
CACHE_POST_DSTORE()
/* Write the zero pattern to the test area */
CACHE_POST_MEMSET(0)
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
/* Read the test area */
CACHE_POST_CHECK()
mr r3, r13
mtlr r9
blr
/*
* Load the test instructions into the instruction cache.
* Replace the test instructions.
* Check that the original instructions are executed.
*/
.global cache_post_test5
cache_post_test5:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WT()
CACHE_POST_IINVALIDATE()
/* Compute r13 = cache_post_test_inst */
bl cache_post_test5_reloc
cache_post_test5_reloc:
mflr r13
lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
add r13, r13, r0
/* Copy the test instructions to the test area */
lwz r0, 0(r13)
stw r0, 0(r11)
lwz r0, 8(r13)
stw r0, 4(r11)
sync
/* Invalidate the cache line */
icbi r0, r11
sync
isync
/* Execute the test instructions */
mtlr r11
blrl
/* Replace the test instruction */
lwz r0, 4(r13)
stw r0, 0(r11)
sync
/* Do not invalidate the cache line */
isync
/* Execute the test instructions */
mtlr r11
blrl
mr r13, r3
CACHE_POST_IINVALIDATE()
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
mr r3, r13
mtlr r9
blr
/*
* Load the test instructions into the instruction cache.
* Replace the test instructions and invalidate the cache.
* Check that the replaced instructions are executed.
*/
.global cache_post_test6
cache_post_test6:
mflr r9
mr r10, r3 /* tlb */
mr r11, r4 /* p */
mr r12, r5 /* size */
CACHE_POST_WT()
CACHE_POST_IINVALIDATE()
/* Compute r13 = cache_post_test_inst */
bl cache_post_test6_reloc
cache_post_test6_reloc:
mflr r13
lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
add r13, r13, r0
/* Copy the test instructions to the test area */
lwz r0, 4(r13)
stw r0, 0(r11)
lwz r0, 8(r13)
stw r0, 4(r11)
sync
/* Invalidate the cache line */
icbi r0, r11
sync
isync
/* Execute the test instructions */
mtlr r11
blrl
/* Replace the test instruction */
lwz r0, 0(r13)
stw r0, 0(r11)
sync
/* Invalidate the cache line */
icbi r0, r11
sync
isync
/* Execute the test instructions */
mtlr r11
blrl
mr r13, r3
CACHE_POST_IINVALIDATE()
CACHE_POST_DINVALIDATE()
CACHE_POST_DISABLE()
mr r3, r13
mtlr r9
blr
/* Test instructions.
*/
cache_post_test_inst:
li r3, 0
li r3, -1
blr
#endif /* CONFIG_POST & CFG_POST_CACHE */
#endif /* CONFIG_POST */

395
post/cpu/ppc4xx/ether.c Normal file
View file

@ -0,0 +1,395 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* Ethernet test
*
* The Ethernet Media Access Controllers (EMAC) are tested in the
* internal loopback mode.
* The controllers are configured accordingly and several packets
* are transmitted. The configurable test parameters are:
* MIN_PACKET_LENGTH - minimum size of packet to transmit
* MAX_PACKET_LENGTH - maximum size of packet to transmit
* TEST_NUM - number of tests
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_ETHER
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <405_mal.h>
#include <ppc4xx_enet.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
#define MIN_PACKET_LENGTH 64
#define MAX_PACKET_LENGTH 256
#define TEST_NUM 1
static volatile mal_desc_t tx __cacheline_aligned;
static volatile mal_desc_t rx __cacheline_aligned;
static char *tx_buf;
static char *rx_buf;
static void ether_post_init (int devnum, int hw_addr)
{
int i;
unsigned mode_reg;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
sys_info_t sysinfo;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr (sdr_mfr, mfr);
sync ();
#endif
/* reset emac */
out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
sync ();
for (i = 0;; i++) {
if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
break;
if (i >= 1000) {
printf ("Timeout resetting EMAC\n");
break;
}
udelay (1000);
}
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Whack the M1 register */
mode_reg = 0x0;
if (sysinfo.freqOPB <= 50000000);
else if (sysinfo.freqOPB <= 66666667)
mode_reg |= EMAC_M1_OBCI_66;
else if (sysinfo.freqOPB <= 83333333)
mode_reg |= EMAC_M1_OBCI_83;
else if (sysinfo.freqOPB <= 100000000)
mode_reg |= EMAC_M1_OBCI_100;
else
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | 0x00330000);
#else
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
if (get_pvr() == PVR_440GP_RB) {
mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
}
#endif
/* setup buffer descriptors */
tx.ctrl = MAL_TX_CTRL_WRAP;
tx.data_len = 0;
tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
rx.data_len = 0;
rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, &tx);
#else
mtdcr (maltxctp1r, &tx);
#endif
#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
#endif
mtdcr (malrxctp1r, &rx);
/* set RX buffer size */
mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
break;
case 0:
default:
/* setup MAL tx & rx channel pointers */
#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
#endif
mtdcr (maltxctp0r, &tx);
mtdcr (malrxctp0r, &rx);
/* set RX buffer size */
mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
break;
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
#endif
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
/* set internal loopback mode */
out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
EMAC_M1_MF_100MBPS | EMAC_M1_IST |
in32 (EMAC_M1));
/* set transmit enable & receive enable */
out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
/* enable broadcast address */
out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
/* set transmit request threshold register */
out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
#else
/* 405s have a 16 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */
out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
out32 (EMAC_TXM0 + hw_addr, 0x00000003);
/* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
sync ();
}
static void ether_post_halt (int devnum, int hw_addr)
{
int i = 0;
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned long mfr;
#endif
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
#else
mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
#endif
mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
/* wait for reset */
while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
if (i++ >= 1000)
break;
udelay (1000);
}
/* emac reset */
out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr (sdr_mfr, mfr);
#endif
}
static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
{
int i = 0;
while (tx.ctrl & MAL_TX_CTRL_READY) {
if (i++ > 100) {
printf ("TX timeout\n");
return;
}
udelay (1000);
}
tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
tx.data_len = length;
memcpy (tx.data_ptr, packet, length);
sync ();
out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
sync ();
}
static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
{
int length;
int i = 0;
while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
if (i++ > 100) {
printf ("RX timeout\n");
return 0;
}
udelay (1000);
}
length = rx.data_len - 4;
if (length <= max_length)
memcpy(packet, rx.data_ptr, length);
sync ();
rx.ctrl |= MAL_RX_CTRL_EMPTY;
sync ();
return length;
}
/*
* Test routines
*/
static void packet_fill (char *packet, int length)
{
char c = (char) length;
int i;
/* set up ethernet header */
memset (packet, 0xff, 14);
for (i = 14; i < length; i++) {
packet[i] = c++;
}
}
static int packet_check (char *packet, int length)
{
char c = (char) length;
int i;
for (i = 14; i < length; i++) {
if (packet[i] != c++)
return -1;
}
return 0;
}
static int test_ctlr (int devnum, int hw_addr)
{
int res = -1;
char packet_send[MAX_PACKET_LENGTH];
char packet_recv[MAX_PACKET_LENGTH];
int length;
int i;
int l;
ether_post_init (devnum, hw_addr);
for (i = 0; i < TEST_NUM; i++) {
for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
packet_fill (packet_send, l);
ether_post_send (devnum, hw_addr, packet_send, l);
length = ether_post_recv (devnum, hw_addr, packet_recv,
sizeof (packet_recv));
if (length != l || packet_check (packet_recv, length) < 0) {
goto Done;
}
}
}
res = 0;
Done:
ether_post_halt (devnum, hw_addr);
if (res != 0) {
post_log ("EMAC%d test failed\n", devnum);
}
return res;
}
int ether_post_test (int flags)
{
int res = 0;
/* Allocate tx & rx packet buffers */
tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
if (!tx_buf || !rx_buf) {
printf ("Failed to allocate packet buffers\n");
res = -1;
goto out_free;
}
/* EMAC0 */
if (test_ctlr (0, 0))
res = -1;
/* EMAC1 */
if (test_ctlr (1, 0x100))
res = -1;
out_free:
free (tx_buf);
free (rx_buf);
return res;
}
#endif /* CONFIG_POST & CFG_POST_ETHER */
#endif /* CONFIG_POST */

10
post/cpu/ppc4xx/fpu.c
View file

@ -1,5 +1,8 @@
/*
* Copyright (C) 2007 Wolfgang Denk <wd@denx.de>
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Sergei Poselenov <sposelenov@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -34,7 +37,7 @@ int fpu_status(void)
{
if (mfspr(ccr0) & CCR0_DAPUIB)
return 0; /* Disabled */
else
else
return 1; /* Enabled */
}
@ -51,5 +54,6 @@ void fpu_enable(void)
mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
mtmsr(mfmsr() | MSR_FP);
}
#endif
#endif
#endif /* CONFIG_POST */

41
post/cpu/ppc4xx/spr.c
View file

@ -2,6 +2,8 @@
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -39,6 +41,8 @@
#if CONFIG_POST & CFG_POST_SPR
#include <asm/processor.h>
static struct
{
int number;
@ -60,8 +64,10 @@ static struct
{0x113, "SPRG3", 0x00000000, 0x00000000},
{0x11f, "PVR", 0x00000000, 0x00000000},
/* Additional Special-Purpose Registers */
/* Additional Special-Purpose Registers.
* The values must match the initialization
* values from cpu/ppc4xx/start.S
*/
{0x30, "PID", 0x00000000, 0x00000000},
{0x3a, "CSRR0", 0x00000000, 0x00000000},
{0x3b, "CSRR1", 0x00000000, 0x00000000},
@ -90,22 +96,22 @@ static struct
{0x13f, "DVC2", 0x00000000, 0x00000000},
{0x150, "TSR", 0x00000000, 0x00000000},
{0x154, "TCR", 0x00000000, 0x00000000},
{0x190, "IVOR0", 0x00000000, 0x00000000},
{0x191, "IVOR1", 0x00000000, 0x00000000},
{0x192, "IVOR2", 0x00000000, 0x00000000},
{0x193, "IVOR3", 0x00000000, 0x00000000},
{0x194, "IVOR4", 0x00000000, 0x00000000},
{0x195, "IVOR5", 0x00000000, 0x00000000},
{0x196, "IVOR6", 0x00000000, 0x00000000},
{0x197, "IVOR7", 0x00000000, 0x00000000},
{0x198, "IVOR8", 0x00000000, 0x00000000},
{0x190, "IVOR0", 0x0000fff0, 0x00000100},
{0x191, "IVOR1", 0x0000fff0, 0x00000200},
{0x192, "IVOR2", 0x0000fff0, 0x00000300},
{0x193, "IVOR3", 0x0000fff0, 0x00000400},
{0x194, "IVOR4", 0x0000fff0, 0x00000500},
{0x195, "IVOR5", 0x0000fff0, 0x00000600},
{0x196, "IVOR6", 0x0000fff0, 0x00000700},
{0x197, "IVOR7", 0x0000fff0, 0x00000800},
{0x198, "IVOR8", 0x0000fff0, 0x00000c00},
{0x199, "IVOR9", 0x00000000, 0x00000000},
{0x19a, "IVOR10", 0x00000000, 0x00000000},
{0x19a, "IVOR10", 0x0000fff0, 0x00000900},
{0x19b, "IVOR11", 0x00000000, 0x00000000},
{0x19c, "IVOR12", 0x00000000, 0x00000000},
{0x19d, "IVOR13", 0x00000000, 0x00000000},
{0x19e, "IVOR14", 0x00000000, 0x00000000},
{0x19f, "IVOR15", 0x00000000, 0x00000000},
{0x19d, "IVOR13", 0x0000fff0, 0x00001300},
{0x19e, "IVOR14", 0x0000fff0, 0x00001400},
{0x19f, "IVOR15", 0x0000fff0, 0x00002000},
{0x23a, "MCSRR0", 0x00000000, 0x00000000},
{0x23b, "MCSRR1", 0x00000000, 0x00000000},
{0x23c, "MCSR", 0x00000000, 0x00000000},
@ -126,8 +132,8 @@ static struct
{0x395, "DTV1", 0x00000000, 0x00000000},
{0x396, "DTV2", 0x00000000, 0x00000000},
{0x397, "DTV3", 0x00000000, 0x00000000},
{0x398, "DVLIM", 0x00000000, 0x00000000},
{0x399, "IVLIM", 0x00000000, 0x00000000},
{0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
{0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
{0x39b, "RSTCFG", 0x00000000, 0x00000000},
{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
@ -172,5 +178,6 @@ int spr_post_test (int flags)
return ret;
}
#endif /* CONFIG_POST & CFG_POST_SPR */
#endif /* CONFIG_POST */

3
post/cpu/ppc4xx/uart.c
View file

@ -2,6 +2,8 @@
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -210,5 +212,4 @@ int uart_post_test (int flags)
}
#endif /* CONFIG_POST & CFG_POST_UART */
#endif /* CONFIG_POST */

9
post/cpu/ppc4xx/watchdog.c
View file

@ -2,6 +2,8 @@
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Igor Lisitsin <igor@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -36,17 +38,18 @@
#ifdef CONFIG_POST
#include <post.h>
#include <watchdog.h>
#if CONFIG_POST & CFG_POST_WATCHDOG
#include <watchdog.h>
int watchdog_post_test (int flags)
{
if (flags & POST_REBOOT) {
/* Test passed */
return 0;
} else {
}
else {
/* 10-second delay */
int ints = disable_interrupts ();
ulong base = post_time_ms (0);

2
post/drivers/Makefile
View file

@ -26,6 +26,6 @@ SUBDIRS =
LIB = libpostdrivers.a
COBJS = cache.o i2c.o memory.o rtc.o
COBJS = i2c.o memory.o rtc.o
include $(TOPDIR)/post/rules.mk

1
post/lib_ppc/Makefile
View file

@ -21,6 +21,7 @@
# MA 02111-1307 USA
#
SUBDIRS = fpu
LIB = libpostppc.a

62
post/lib_ppc/fpu/20001122-1.c Normal file
View file

@ -0,0 +1,62 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
int fpu_post_test_math1 (void)
{
volatile double a, *p;
double c, d;
volatile double b;
d = 1.0;
p = &b;
do
{
c = d;
d = c * 0.5;
b = 1 + d;
} while (b != 1.0);
a = 1.0 + c;
if (a == 1.0) {
post_log ("Error in FPU math1 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

66
post/lib_ppc/fpu/20010114-2.c Normal file
View file

@ -0,0 +1,66 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
static float rintf (float x)
{
volatile float TWO23 = 8388608.0;
if (__builtin_fabs (x) < TWO23)
{
if (x > 0.0)
{
x += TWO23;
x -= TWO23;
}
else if (x < 0.0)
{
x = TWO23 - x;
x = -(x - TWO23);
}
}
return x;
}
int fpu_post_test_math2 (void)
{
if (rintf (-1.5) != -2.0) {
post_log ("Error in FPU math2 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

54
post/lib_ppc/fpu/20010226-1.c Normal file
View file

@ -0,0 +1,54 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
int fpu_post_test_math3 (void)
{
volatile long double dfrom = 1.1;
volatile long double m1;
volatile long double m2;
volatile unsigned long mant_long;
m1 = dfrom / 2.0;
m2 = m1 * 4294967296.0;
mant_long = ((unsigned long) m2) & 0xffffffff;
if (mant_long != 0x8ccccccc) {
post_log ("Error in FPU math3 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

60
post/lib_ppc/fpu/980619-1.c Normal file
View file

@ -0,0 +1,60 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
int fpu_post_test_math4 (void)
{
volatile float reale = 1.0f;
volatile float oneplus;
int i;
if (sizeof (float) != 4)
return 0;
for (i = 0; ; i++)
{
oneplus = 1.0f + reale;
if (oneplus == 1.0f)
break;
reale = reale / 2.0f;
}
/* Assumes ieee754 accurate arithmetic above. */
if (i != 24) {
post_log ("Error in FPU math4 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

32
post/lib_ppc/fpu/Makefile Normal file
View file

@ -0,0 +1,32 @@
#
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
LIB = libpostppcfpu.a
COBJS += fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
COBJS += acc1.o compare-fp-1.o mul-subnormal-single-1.o
include $(TOPDIR)/post/rules.mk
CFLAGS += -mhard-float -fkeep-inline-functions

57
post/lib_ppc/fpu/acc1.c Normal file
View file

@ -0,0 +1,57 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
static double func (const double *array)
{
double d = *array;
if (d == 0.0)
return d;
else
return d + func (array + 1);
}
int fpu_post_test_math5 (void)
{
double values[] = { 0.1e-100, 1.0, -1.0, 0.0 };
if (func (values) != 0.1e-100) {
post_log ("Error in FPU math5 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

225
post/lib_ppc/fpu/compare-fp-1.c Normal file
View file

@ -0,0 +1,225 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Test for correctness of composite floating-point comparisons.
* Written by Paolo Bonzini, 26th May 2004.
* This file is originally a part of the GCC testsuite.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
static int failed;
#define TEST(c) if ((c) != ok) failed++
#define ORD(a, b) (!__builtin_isunordered ((a), (b)))
#define UNORD(a, b) (__builtin_isunordered ((a), (b)))
#define UNEQ(a, b) (__builtin_isunordered ((a), (b)) || ((a) == (b)))
#define UNLT(a, b) (__builtin_isunordered ((a), (b)) || ((a) < (b)))
#define UNLE(a, b) (__builtin_isunordered ((a), (b)) || ((a) <= (b)))
#define UNGT(a, b) (__builtin_isunordered ((a), (b)) || ((a) > (b)))
#define UNGE(a, b) (__builtin_isunordered ((a), (b)) || ((a) >= (b)))
#define LTGT(a, b) (__builtin_islessgreater ((a), (b)))
static float pinf;
static float ninf;
static float NaN;
static void iuneq (float x, float y, int ok)
{
TEST (UNEQ (x, y));
TEST (!LTGT (x, y));
TEST (UNLE (x, y) && UNGE (x,y));
}
static void ieq (float x, float y, int ok)
{
TEST (ORD (x, y) && UNEQ (x, y));
}
static void iltgt (float x, float y, int ok)
{
TEST (!UNEQ (x, y)); /* Not optimizable. */
TEST (LTGT (x, y)); /* Same, __builtin_islessgreater does not trap. */
TEST (ORD (x, y) && (UNLT (x, y) || UNGT (x,y)));
}
static void ine (float x, float y, int ok)
{
TEST (UNLT (x, y) || UNGT (x, y));
}
static void iunlt (float x, float y, int ok)
{
TEST (UNLT (x, y));
TEST (UNORD (x, y) || (x < y));
}
static void ilt (float x, float y, int ok)
{
TEST (ORD (x, y) && UNLT (x, y)); /* Not optimized */
TEST ((x <= y) && (x != y));
TEST ((x <= y) && (y != x));
TEST ((x != y) && (x <= y)); /* Not optimized */
TEST ((y != x) && (x <= y)); /* Not optimized */
}
static void iunle (float x, float y, int ok)
{
TEST (UNLE (x, y));
TEST (UNORD (x, y) || (x <= y));
}
static void ile (float x, float y, int ok)
{
TEST (ORD (x, y) && UNLE (x, y)); /* Not optimized */
TEST ((x < y) || (x == y));
TEST ((y > x) || (x == y));
TEST ((x == y) || (x < y)); /* Not optimized */
TEST ((y == x) || (x < y)); /* Not optimized */
}
static void iungt (float x, float y, int ok)
{
TEST (UNGT (x, y));
TEST (UNORD (x, y) || (x > y));
}
static void igt (float x, float y, int ok)
{
TEST (ORD (x, y) && UNGT (x, y)); /* Not optimized */
TEST ((x >= y) && (x != y));
TEST ((x >= y) && (y != x));
TEST ((x != y) && (x >= y)); /* Not optimized */
TEST ((y != x) && (x >= y)); /* Not optimized */
}
static void iunge (float x, float y, int ok)
{
TEST (UNGE (x, y));
TEST (UNORD (x, y) || (x >= y));
}
static void ige (float x, float y, int ok)
{
TEST (ORD (x, y) && UNGE (x, y)); /* Not optimized */
TEST ((x > y) || (x == y));
TEST ((y < x) || (x == y));
TEST ((x == y) || (x > y)); /* Not optimized */
TEST ((y == x) || (x > y)); /* Not optimized */
}
int fpu_post_test_math6 (void)
{
pinf = __builtin_inf ();
ninf = -__builtin_inf ();
NaN = __builtin_nan ("");
iuneq (ninf, pinf, 0);
iuneq (NaN, NaN, 1);
iuneq (pinf, ninf, 0);
iuneq (1, 4, 0);
iuneq (3, 3, 1);
iuneq (5, 2, 0);
ieq (1, 4, 0);
ieq (3, 3, 1);
ieq (5, 2, 0);
iltgt (ninf, pinf, 1);
iltgt (NaN, NaN, 0);
iltgt (pinf, ninf, 1);
iltgt (1, 4, 1);
iltgt (3, 3, 0);
iltgt (5, 2, 1);
ine (1, 4, 1);
ine (3, 3, 0);
ine (5, 2, 1);
iunlt (NaN, ninf, 1);
iunlt (pinf, NaN, 1);
iunlt (pinf, ninf, 0);
iunlt (pinf, pinf, 0);
iunlt (ninf, ninf, 0);
iunlt (1, 4, 1);
iunlt (3, 3, 0);
iunlt (5, 2, 0);
ilt (1, 4, 1);
ilt (3, 3, 0);
ilt (5, 2, 0);
iunle (NaN, ninf, 1);
iunle (pinf, NaN, 1);
iunle (pinf, ninf, 0);
iunle (pinf, pinf, 1);
iunle (ninf, ninf, 1);
iunle (1, 4, 1);
iunle (3, 3, 1);
iunle (5, 2, 0);
ile (1, 4, 1);
ile (3, 3, 1);
ile (5, 2, 0);
iungt (NaN, ninf, 1);
iungt (pinf, NaN, 1);
iungt (pinf, ninf, 1);
iungt (pinf, pinf, 0);
iungt (ninf, ninf, 0);
iungt (1, 4, 0);
iungt (3, 3, 0);
iungt (5, 2, 1);
igt (1, 4, 0);
igt (3, 3, 0);
igt (5, 2, 1);
iunge (NaN, ninf, 1);
iunge (pinf, NaN, 1);
iunge (ninf, pinf, 0);
iunge (pinf, pinf, 1);
iunge (ninf, ninf, 1);
iunge (1, 4, 0);
iunge (3, 3, 1);
iunge (5, 2, 1);
ige (1, 4, 0);
ige (3, 3, 1);
ige (5, 2, 1);
if (failed) {
post_log ("Error in FPU math6 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

92
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@ -0,0 +1,92 @@
/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Author: Sergei Poselenov <sposelenov@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* FPU test
*
* This test checks the arithmetic logic unit (ALU) of CPU.
* It tests independently various groups of instructions using
* run-time modification of the code to reduce the memory footprint.
* For more details refer to post/cpu/ *.c files.
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
#include <watchdog.h>
extern int fpu_status (void);
extern void fpu_enable (void);
extern void fpu_disable (void);
extern int fpu_post_test_math1 (void);
extern int fpu_post_test_math2 (void);
extern int fpu_post_test_math3 (void);
extern int fpu_post_test_math4 (void);
extern int fpu_post_test_math5 (void);
extern int fpu_post_test_math6 (void);
extern int fpu_post_test_math7 (void);
int fpu_post_test (int flags)
{
int fpu = fpu_status ();
int ret = 0;
WATCHDOG_RESET ();
if (!fpu)
fpu_enable ();
if (ret == 0)
ret = fpu_post_test_math1 ();
if (ret == 0)
ret = fpu_post_test_math2 ();
if (ret == 0)
ret = fpu_post_test_math3 ();
if (ret == 0)
ret = fpu_post_test_math4 ();
if (ret == 0)
ret = fpu_post_test_math5 ();
if (ret == 0)
ret = fpu_post_test_math6 ();
if (ret == 0)
ret = fpu_post_test_math7 ();
if (!fpu)
fpu_disable ();
WATCHDOG_RESET ();
return ret;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */

103
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/*
* Copyright (C) 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file is originally a part of the GCC testsuite.
* Check that certain subnormal numbers (formerly known as denormalized
* numbers) are rounded to within 0.5 ulp. PR other/14354.
*/
#include <common.h>
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_FPU
union uf
{
unsigned int u;
float f;
};
static float
u2f (unsigned int v)
{
union uf u;
u.u = v;
return u.f;
}
static unsigned int
f2u (float v)
{
union uf u;
u.f = v;
return u.u;
}
static int ok = 1;
static void
tstmul (unsigned int ux, unsigned int uy, unsigned int ur)
{
float x = u2f (ux);
float y = u2f (uy);
if (f2u (x * y) != ur)
/* Set a variable rather than aborting here, to simplify tracing when
several computations are wrong. */
ok = 0;
}
/* We don't want to make this const and static, or else we risk inlining
causing the test to fold as constants at compile-time. */
struct
{
unsigned int p1, p2, res;
} static volatile expected[] =
{
{0xfff, 0x3f800400, 0xfff},
{0xf, 0x3fc88888, 0x17},
{0xf, 0x3f844444, 0xf}
};
int fpu_post_test_math7 (void)
{
unsigned int i;
for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++)
{
tstmul (expected[i].p1, expected[i].p2, expected[i].res);
tstmul (expected[i].p2, expected[i].p1, expected[i].res);
}
if (!ok) {
post_log ("Error in FPU math7 test\n");
return -1;
}
return 0;
}
#endif /* CONFIG_POST & CFG_POST_FPU */
#endif /* CONFIG_POST */