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https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
Cleanup for CMC_PU2 board
This commit is contained in:
wdenk
parent
96085e347d
commit
45ea3fca4a
4 changed files with 57 additions and 70 deletions
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@ -29,6 +29,10 @@
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#include <common.h>
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#ifndef CFG_ENV_ADDR
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
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#endif
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*
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@ -194,12 +198,12 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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switch (addr[0] & 0xff) {
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case (uchar)AMD_MANUFACT:
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printf ("Manufacturer: AMD (Spansion)\n");
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debug ("Manufacturer: AMD (Spansion)\n");
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info->flash_id = FLASH_MAN_AMD;
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break;
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case (uchar)INTEL_MANUFACT:
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printf ("Manufacturer: Intel (not supported yet)\n");
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debug ("Manufacturer: Intel (not supported yet)\n");
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info->flash_id = FLASH_MAN_INTEL;
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break;
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@ -214,7 +218,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
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case AMD_ID_MIRROR:
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printf ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
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debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
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addr[14], addr[15]);
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switch(addr[14] & 0xffff) {
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@ -225,7 +229,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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info->sector_count = 0;
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info->size = 0;
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} else {
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printf ("Chip: S29GL064M-R6\n");
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debug ("Chip: S29GL064M-R6\n");
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info->flash_id += FLASH_S29GL064M;
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info->sector_count = 128;
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info->size = 0x00800000;
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@ -265,16 +269,16 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
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int flag, prot, sect, ssect, l_sect;
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ulong start, now, last;
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printf ("flash_erase: first: %d last: %d\n", s_first, s_last);
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debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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}
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return 1;
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}
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}
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if ((info->flash_id == FLASH_UNKNOWN) ||
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(info->flash_id > FLASH_AMD_COMP)) {
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@ -64,9 +64,9 @@ SECTIONS
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.sdata : { *(.sdata) }
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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@ -33,7 +33,7 @@
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#include <at91rm9200_i2c.h>
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static int debug = 0;
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/* define DEBUG */
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/*
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* Poll the i2c status register until the specified bit is set.
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@ -79,15 +79,13 @@ at91_xfer(unsigned char chip, unsigned int addr, int alen,
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twi->TWI_CR = AT91C_TWI_STOP;
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/* Wait until transfer is finished */
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if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
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if (debug)
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printf("at91_i2c: timeout 1\n");
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debug ("at91_i2c: timeout 1\n");
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return 1;
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}
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*buf++ = twi->TWI_RHR;
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}
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if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
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if (debug)
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printf("at91_i2c: timeout 2\n");
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debug ("at91_i2c: timeout 2\n");
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return 1;
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}
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} else {
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@ -97,15 +95,13 @@ at91_xfer(unsigned char chip, unsigned int addr, int alen,
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if (!length)
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twi->TWI_CR = AT91C_TWI_STOP;
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if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
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if (debug)
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printf("at91_i2c: timeout 3\n");
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debug ("at91_i2c: timeout 3\n");
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return 1;
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}
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}
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/* Wait until transfer is finished */
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if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
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if (debug)
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printf("at91_i2c: timeout 4\n");
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debug ("at91_i2c: timeout 4\n");
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return 1;
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}
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}
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@ -190,7 +186,7 @@ i2c_init(int speed, int slaveaddr)
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/* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
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twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
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printf("Found AT91 i2c\n");
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debug ("Found AT91 i2c\n");
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return;
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}
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#endif /* CONFIG_HARD_I2C */
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@ -13,7 +13,7 @@
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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@ -38,7 +38,7 @@
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
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#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
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#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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@ -58,7 +58,7 @@
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BAUDRATE 9600
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#define CFG_AT91C_BRGR_DIVISOR 450 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
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@ -78,11 +78,11 @@
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#define CONFIG_HARD_I2C
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#ifdef CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 0 /* not used */
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#define CFG_I2C_SLAVE 0 /* not used */
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#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
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#define CFG_I2C_RTC_ADDR 0x32
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_I2C_SPEED 0 /* not used */
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#define CFG_I2C_SLAVE 0 /* not used */
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#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
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#define CFG_I2C_RTC_ADDR 0x32
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW
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#endif
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@ -90,44 +90,33 @@
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#define CFG_LONGHELP
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#define CONFIG_BOOTDELAY 3
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/* #define CONFIG_ENV_OVERWRITE 1 */
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#ifdef CONFIG_HARD_I2C
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#define CONFIG_COMMANDS \
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((CONFIG_CMD_DFL | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE | \
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CFG_CMD_EEPROM | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_BDI | \
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CFG_CMD_IMI | \
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CFG_CMD_AUTOSCRIPT | \
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CFG_CMD_FPGA | \
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CFG_CMD_MISC | \
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CFG_CMD_LOADS ))
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((CONFIG_CMD_DFL | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE | \
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CFG_CMD_EEPROM | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_FPGA | CFG_CMD_MISC) )
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#else
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#define CONFIG_COMMANDS \
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((CONFIG_CMD_DFL | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_BDI | \
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CFG_CMD_IMI | \
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CFG_CMD_AUTOSCRIPT | \
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CFG_CMD_FPGA | \
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CFG_CMD_MISC | \
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CFG_CMD_LOADS ))
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((CONFIG_CMD_DFL | \
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CFG_CMD_DHCP ) & \
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~(CFG_CMD_FPGA | CFG_CMD_MISC) )
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#define CONFIG_TIMESTAMP
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#endif
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/* still about 20 kB free with this defined */
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#define CFG_LONGHELP
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
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#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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@ -138,34 +127,32 @@
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#define CONFIG_HAS_DATAFLASH 1
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#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
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#define CFG_MAX_DATAFLASH_BANKS 2
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#define CFG_MAX_DATAFLASH_PAGES 16384
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#define CFG_MAX_DATAFLASH_BANKS 2
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#define CFG_MAX_DATAFLASH_PAGES 16384
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#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
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#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
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#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
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#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
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#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
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#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
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#define CFG_U_BOOT_BASE PHYS_FLASH_1
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#define CFG_U_BOOT_SIZE 0x20000 /* 128 KBytes */
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CFG_PROMPT "cmc> " /* Monitor Command Prompt */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_MAXARGS 32 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#ifndef __ASSEMBLY__
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@ -179,13 +166,13 @@
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struct bd_info_ext {
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/* helper variable for board environment handling
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*
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* env_crc_valid == 0 => uninitialised
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* env_crc_valid > 0 => environment crc in flash is valid
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* env_crc_valid < 0 => environment crc in flash is invalid
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* env_crc_valid == 0 => uninitialised
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* env_crc_valid > 0 => environment crc in flash is valid
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* env_crc_valid < 0 => environment crc in flash is invalid
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*/
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int env_crc_valid;
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};
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#endif
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#endif /* __ASSEMBLY__ */
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#define CFG_HZ 1000
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#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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@ -197,4 +184,4 @@ struct bd_info_ext {
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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#endif /* __CONFIG_H */
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