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rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

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The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Xu Ziyuan 2017-04-16 17:44:45 +08:00 committed by Simon Glass
parent 7a25a63c13
commit 45112271ef
1 changed files with 12 additions and 0 deletions
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12
drivers/clk/rockchip/clk_rk3288.c
View file

@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
switch (periph) { switch (periph) {
case HCLK_EMMC: case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]); con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break; break;
case HCLK_SDMMC: case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]); con = readl(&cru->cru_clksel_con[11]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break; break;
case HCLK_SDIO0: case HCLK_SDIO0:
case SCLK_SDIO0:
con = readl(&cru->cru_clksel_con[12]); con = readl(&cru->cru_clksel_con[12]);
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
} }
switch (periph) { switch (periph) {
case HCLK_EMMC: case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12], rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_PLL_MASK << EMMC_PLL_SHIFT | EMMC_PLL_MASK << EMMC_PLL_SHIFT |
EMMC_DIV_MASK << EMMC_DIV_SHIFT, EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
(src_clk_div - 1) << EMMC_DIV_SHIFT); (src_clk_div - 1) << EMMC_DIV_SHIFT);
break; break;
case HCLK_SDMMC: case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11], rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK << MMC0_PLL_SHIFT | MMC0_PLL_MASK << MMC0_PLL_SHIFT |
MMC0_DIV_MASK << MMC0_DIV_SHIFT, MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
(src_clk_div - 1) << MMC0_DIV_SHIFT); (src_clk_div - 1) << MMC0_DIV_SHIFT);
break; break;
case HCLK_SDIO0: case HCLK_SDIO0:
case SCLK_SDIO0:
rk_clrsetreg(&cru->cru_clksel_con[12], rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case HCLK_EMMC: case HCLK_EMMC:
case HCLK_SDMMC: case HCLK_SDMMC:
case HCLK_SDIO0: case HCLK_SDIO0:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO0:
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break; break;
case SCLK_SPI0: case SCLK_SPI0:
@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
case HCLK_EMMC: case HCLK_EMMC:
case HCLK_SDMMC: case HCLK_SDMMC:
case HCLK_SDIO0: case HCLK_SDIO0:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO0:
new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
break; break;
case SCLK_SPI0: case SCLK_SPI0: