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driver:usb:s3c_udc: add support for Exynos4x12
This patch add new defines for usb phy for Exynos4x12. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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31e0bd6974
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2 changed files with 12 additions and 2 deletions
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@ -226,6 +226,11 @@ struct s3c_usbotg_reg {
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#define CLK_SEL_12MHZ (0x2 << 0)
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#define CLK_SEL_48MHZ (0x0 << 0)
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#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
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#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
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#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
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#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
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/* Device Configuration Register DCFG */
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#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
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#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
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@ -167,8 +167,13 @@ void otg_phy_init(struct s3c_udc *dev)
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writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
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&~FORCE_SUSPEND_0), &phy->phypwr);
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writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
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CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
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if (s5p_cpu_id == 0x4412)
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writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
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EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
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&phy->phyclk); /* PLL 24Mhz */
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else
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writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
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CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
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writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
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| PHY_SW_RST0, &phy->rstcon);
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