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https://github.com/AsahiLinux/u-boot
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i2c: synquacer: SNI Synquacer I2C controller
Add driver for class of I2C controllers found on Socionext Synquacer platform. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Jassi Brar
Tom Rini
parent
971a344285
commit
4483fbab81
3 changed files with 346 additions and 0 deletions
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@ -455,6 +455,13 @@ config SYS_I2C_STM32F7
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_ Optional clock stretching
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_ Software reset
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config SYS_I2C_SYNQUACER
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bool "Socionext SynQuacer I2C controller"
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depends on ARCH_SYNQUACER && DM_I2C
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help
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Support for Socionext Synquacer I2C controller. This I2C controller
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will be used for RTC and LS-connector on DeveloperBox.
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config SYS_I2C_TEGRA
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bool "NVIDIA Tegra internal I2C controller"
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depends on ARCH_TEGRA
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@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
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obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
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obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
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obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
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338
drivers/i2c/synquacer_i2c.c
Normal file
338
drivers/i2c/synquacer_i2c.c
Normal file
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@ -0,0 +1,338 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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*/
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <clk.h>
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#define REG_BSR 0x0
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#define REG_BCR 0x4
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#define REG_CCR 0x8
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#define REG_ADR 0xc
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#define REG_DAR 0x10
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#define REG_CSR 0x14
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#define REG_FSR 0x18
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#define REG_BC2R 0x1c
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/* I2C register bit definitions */
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#define BSR_FBT BIT(0) // First Byte Transfer
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#define BSR_GCA BIT(1) // General Call Address
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#define BSR_AAS BIT(2) // Address as Slave
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#define BSR_TRX BIT(3) // Transfer/Receive
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#define BSR_LRB BIT(4) // Last Received Bit
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#define BSR_AL BIT(5) // Arbitration Lost
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#define BSR_RSC BIT(6) // Repeated Start Cond.
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#define BSR_BB BIT(7) // Bus Busy
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#define BCR_INT BIT(0) // Interrupt
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#define BCR_INTE BIT(1) // Interrupt Enable
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#define BCR_GCAA BIT(2) // Gen. Call Access Ack.
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#define BCR_ACK BIT(3) // Acknowledge
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#define BCR_MSS BIT(4) // Master Slave Select
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#define BCR_SCC BIT(5) // Start Condition Cont.
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#define BCR_BEIE BIT(6) // Bus Error Int Enable
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#define BCR_BER BIT(7) // Bus Error
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#define CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
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#define CCR_EN BIT(5) // Enable
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#define CCR_FM BIT(6) // Speed Mode Select
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#define CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
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#define BC2R_SCLL BIT(0) // SCL Low Drive
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#define BC2R_SDAL BIT(1) // SDA Low Drive
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#define BC2R_SCLS BIT(4) // SCL Status
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#define BC2R_SDAS BIT(5) // SDA Status
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/* PCLK frequency */
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#define BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
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#define I2C_CLK_DEF 62500000
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/* STANDARD MODE frequency */
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#define CLK_MASTER_STD(rate) \
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DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2)
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/* FAST MODE frequency */
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#define CLK_MASTER_FAST(rate) \
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DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3)
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/* (clkrate <= 18000000) */
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/* calculate the value of CS bits in CCR register on standard mode */
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#define CCR_CS_STD_MAX_18M(rate) \
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((CLK_MASTER_STD(rate) - 65) \
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& CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on standard mode */
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#define CSR_CS_STD_MAX_18M(rate) 0x00
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/* calculate the value of CS bits in CCR register on fast mode */
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#define CCR_CS_FAST_MAX_18M(rate) \
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((CLK_MASTER_FAST(rate) - 1) \
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& CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on fast mode */
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#define CSR_CS_FAST_MAX_18M(rate) 0x00
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/* (clkrate > 18000000) */
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/* calculate the value of CS bits in CCR register on standard mode */
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#define CCR_CS_STD_MIN_18M(rate) \
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((CLK_MASTER_STD(rate) - 1) \
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& CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on standard mode */
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#define CSR_CS_STD_MIN_18M(rate) \
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(((CLK_MASTER_STD(rate) - 1) >> 5) \
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& CSR_CS_MASK)
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/* calculate the value of CS bits in CCR register on fast mode */
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#define CCR_CS_FAST_MIN_18M(rate) \
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((CLK_MASTER_FAST(rate) - 1) \
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& CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on fast mode */
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#define CSR_CS_FAST_MIN_18M(rate) \
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(((CLK_MASTER_FAST(rate) - 1) >> 5) \
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& CSR_CS_MASK)
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/* min I2C clock frequency 14M */
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#define MIN_CLK_RATE (14 * 1000000)
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/* max I2C clock frequency 200M */
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#define MAX_CLK_RATE (200 * 1000000)
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/* I2C clock frequency 18M */
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#define CLK_RATE_18M (18 * 1000000)
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#define SPEED_FM 400 // Fast Mode
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#define SPEED_SM 100 // Standard Mode
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DECLARE_GLOBAL_DATA_PTR;
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struct synquacer_i2c {
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void __iomem *base;
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unsigned long pclkrate;
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unsigned long speed_khz;
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};
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static int wait_irq(struct udevice *dev)
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{
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struct synquacer_i2c *i2c = dev_get_priv(dev);
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int timeout = 500000;
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do {
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if (readb(i2c->base + REG_BCR) & BCR_INT)
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return 0;
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} while (timeout--);
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pr_err("%s: timeout\n", __func__);
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return -1;
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}
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static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c,
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int addr, int read)
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{
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u8 bsr, bcr;
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writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR);
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bsr = readb(i2c->base + REG_BSR);
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bcr = readb(i2c->base + REG_BCR);
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if ((bsr & BSR_BB) && !(bcr & BCR_MSS))
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return -EBUSY;
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if (bsr & BSR_BB) {
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writeb(bcr | BCR_SCC, i2c->base + REG_BCR);
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} else {
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if (bcr & BCR_MSS)
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return -EAGAIN;
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/* Start Condition + Enable Interrupts */
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writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR);
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}
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udelay(100);
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return 0;
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}
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static int synquacer_i2c_xfer(struct udevice *bus,
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struct i2c_msg *msg, int nmsgs)
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{
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struct synquacer_i2c *i2c = dev_get_priv(bus);
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u8 bsr, bcr;
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int idx;
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for (; nmsgs > 0; nmsgs--, msg++) {
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synquacer_i2c_xfer_start(i2c, msg->addr, msg->flags & I2C_M_RD);
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if (wait_irq(bus))
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return -EREMOTEIO;
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bsr = readb(i2c->base + REG_BSR);
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if (bsr & BSR_LRB) {
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debug("%s: No ack received\n", __func__);
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return -EREMOTEIO;
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}
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idx = 0;
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do {
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bsr = readb(i2c->base + REG_BSR);
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bcr = readb(i2c->base + REG_BCR);
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if (bcr & BCR_BER) {
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debug("%s: Bus error detected\n", __func__);
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return -EREMOTEIO;
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}
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if ((bsr & BSR_AL) || !(bcr & BCR_MSS)) {
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debug("%s: Arbitration lost\n", __func__);
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return -EREMOTEIO;
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}
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if (msg->flags & I2C_M_RD) {
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bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
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if (idx < msg->len - 1)
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bcr |= BCR_ACK;
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writeb(bcr, i2c->base + REG_BCR);
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if (wait_irq(bus))
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return -EREMOTEIO;
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bsr = readb(i2c->base + REG_BSR);
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if (!(bsr & BSR_FBT))
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msg->buf[idx++] = readb(i2c->base + REG_DAR);
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} else {
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writeb(msg->buf[idx++], i2c->base + REG_DAR);
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bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
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writeb(bcr, i2c->base + REG_BCR);
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if (wait_irq(bus))
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return -EREMOTEIO;
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bsr = readb(i2c->base + REG_BSR);
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if (bsr & BSR_LRB) {
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debug("%s: no ack\n", __func__);
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return -EREMOTEIO;
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}
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}
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} while (idx < msg->len);
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}
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/* Force bus state to idle, terminating any ongoing transfer */
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writeb(0, i2c->base + REG_BCR);
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udelay(100);
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return 0;
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}
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static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
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{
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/* Disable clock */
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writeb(0, i2c->base + REG_CCR);
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writeb(0, i2c->base + REG_CSR);
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/* Set own Address */
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writeb(0, i2c->base + REG_ADR);
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/* Set PCLK frequency */
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writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
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/* clear IRQ (INT=0, BER=0), Interrupt Disable */
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writeb(0, i2c->base + REG_BCR);
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writeb(0, i2c->base + REG_BC2R);
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}
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static int synquacer_i2c_get_bus_speed(struct udevice *bus)
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{
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struct synquacer_i2c *i2c = dev_get_priv(bus);
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return i2c->speed_khz * 1000;
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}
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static int synquacer_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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struct synquacer_i2c *i2c = dev_get_priv(bus);
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u32 rt = i2c->pclkrate;
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u8 ccr_cs, csr_cs;
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/* Set PCLK frequency */
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writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
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if (speed >= SPEED_FM * 1000) {
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i2c->speed_khz = SPEED_FM;
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if (i2c->pclkrate <= CLK_RATE_18M) {
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ccr_cs = CCR_CS_FAST_MAX_18M(rt);
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csr_cs = CSR_CS_FAST_MAX_18M(rt);
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} else {
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ccr_cs = CCR_CS_FAST_MIN_18M(rt);
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csr_cs = CSR_CS_FAST_MIN_18M(rt);
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}
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/* Set Clock and enable, Set fast mode */
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writeb(ccr_cs | CCR_FM | CCR_EN, i2c->base + REG_CCR);
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writeb(csr_cs, i2c->base + REG_CSR);
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} else {
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i2c->speed_khz = SPEED_SM;
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if (i2c->pclkrate <= CLK_RATE_18M) {
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ccr_cs = CCR_CS_STD_MAX_18M(rt);
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csr_cs = CSR_CS_STD_MAX_18M(rt);
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} else {
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ccr_cs = CCR_CS_STD_MIN_18M(rt);
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csr_cs = CSR_CS_STD_MIN_18M(rt);
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}
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/* Set Clock and enable, Set standard mode */
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writeb(ccr_cs | CCR_EN, i2c->base + REG_CCR);
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writeb(csr_cs, i2c->base + REG_CSR);
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}
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return 0;
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}
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static int synquacer_i2c_of_to_plat(struct udevice *bus)
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{
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struct synquacer_i2c *priv = dev_get_priv(bus);
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struct clk ck;
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int ret;
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ret = clk_get_by_index(bus, 0, &ck);
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if (ret < 0) {
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priv->pclkrate = I2C_CLK_DEF;
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} else {
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clk_enable(&ck);
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priv->pclkrate = clk_get_rate(&ck);
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}
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return 0;
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}
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static int synquacer_i2c_probe(struct udevice *bus)
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{
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struct synquacer_i2c *i2c = dev_get_priv(bus);
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i2c->base = dev_read_addr_ptr(bus);
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synquacer_i2c_hw_reset(i2c);
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synquacer_i2c_set_bus_speed(bus, 400000); /* set default speed */
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return 0;
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}
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static const struct dm_i2c_ops synquacer_i2c_ops = {
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.xfer = synquacer_i2c_xfer,
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.set_bus_speed = synquacer_i2c_set_bus_speed,
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.get_bus_speed = synquacer_i2c_get_bus_speed,
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};
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static const struct udevice_id synquacer_i2c_ids[] = {
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{
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.compatible = "socionext,synquacer-i2c",
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},
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{ }
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};
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U_BOOT_DRIVER(sni_synquacer_i2c) = {
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.name = "sni_synquacer_i2c",
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.id = UCLASS_I2C,
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.of_match = synquacer_i2c_ids,
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.of_to_plat = synquacer_i2c_of_to_plat,
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.probe = synquacer_i2c_probe,
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.priv_auto = sizeof(struct synquacer_i2c),
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.ops = &synquacer_i2c_ops,
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};
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