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rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL
The device-tree node for the PMU clk controller assigns to its parent
(i.e. PLL_PPLL) even though this clock currently is set up statically
by an init-function.
In order to avoid unexpected failures, a simple implementation of
set_rate (which accepts requests, but notifies the caller of the
preset frequency in its return value) and get_rate (which always
returns the preset frequency) are added.
Note that this is required for the RK808 PMIC to probe successfully on
the RK3399-Q7, following the support for the assigned-clocks property.
References: commit f4fcba5c5b
("clk: implement clk_set_defaults()")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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1 changed files with 9 additions and 0 deletions
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@ -1246,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
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ulong rate = 0;
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switch (clk->id) {
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case PLL_PPLL:
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return PPLL_HZ;
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case PCLK_RKPWM_PMU:
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rate = rk3399_pwm_get_clk(priv->pmucru);
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break;
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@ -1267,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
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ulong ret = 0;
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switch (clk->id) {
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case PLL_PPLL:
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/*
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* This has already been set up and we don't want/need
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* to change it here. Accept the request though, as the
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* device-tree has this in an 'assigned-clocks' list.
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*/
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return PPLL_HZ;
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case SCLK_I2C0_PMU:
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case SCLK_I2C4_PMU:
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case SCLK_I2C8_PMU:
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