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zynqmp_firmware: Add zynqmp firmware related enums

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Add enums for pm node id's, pm ioctl id's, tapdelay types, dll reset types

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy 2021-08-02 23:20:42 -06:00 committed by Michal Simek
parent 16b593bec7
commit 42e01bf20a
1 changed files with 127 additions and 0 deletions
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127
include/zynqmp_firmware.h
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@ -67,6 +67,99 @@ enum pm_api_id {
PM_API_MAX,
};
enum pm_node_id {
NODE_UNKNOWN = 0,
NODE_APU = 1,
NODE_APU_0 = 2,
NODE_APU_1 = 3,
NODE_APU_2 = 4,
NODE_APU_3 = 5,
NODE_RPU = 6,
NODE_RPU_0 = 7,
NODE_RPU_1 = 8,
NODE_PLD = 9,
NODE_FPD = 10,
NODE_OCM_BANK_0 = 11,
NODE_OCM_BANK_1 = 12,
NODE_OCM_BANK_2 = 13,
NODE_OCM_BANK_3 = 14,
NODE_TCM_0_A = 15,
NODE_TCM_0_B = 16,
NODE_TCM_1_A = 17,
NODE_TCM_1_B = 18,
NODE_L2 = 19,
NODE_GPU_PP_0 = 20,
NODE_GPU_PP_1 = 21,
NODE_USB_0 = 22,
NODE_USB_1 = 23,
NODE_TTC_0 = 24,
NODE_TTC_1 = 25,
NODE_TTC_2 = 26,
NODE_TTC_3 = 27,
NODE_SATA = 28,
NODE_ETH_0 = 29,
NODE_ETH_1 = 30,
NODE_ETH_2 = 31,
NODE_ETH_3 = 32,
NODE_UART_0 = 33,
NODE_UART_1 = 34,
NODE_SPI_0 = 35,
NODE_SPI_1 = 36,
NODE_I2C_0 = 37,
NODE_I2C_1 = 38,
NODE_SD_0 = 39,
NODE_SD_1 = 40,
NODE_DP = 41,
NODE_GDMA = 42,
NODE_ADMA = 43,
NODE_NAND = 44,
NODE_QSPI = 45,
NODE_GPIO = 46,
NODE_CAN_0 = 47,
NODE_CAN_1 = 48,
NODE_EXTERN = 49,
NODE_APLL = 50,
NODE_VPLL = 51,
NODE_DPLL = 52,
NODE_RPLL = 53,
NODE_IOPLL = 54,
NODE_DDR = 55,
NODE_IPI_APU = 56,
NODE_IPI_RPU_0 = 57,
NODE_GPU = 58,
NODE_PCIE = 59,
NODE_PCAP = 60,
NODE_RTC = 61,
NODE_LPD = 62,
NODE_VCU = 63,
NODE_IPI_RPU_1 = 64,
NODE_IPI_PL_0 = 65,
NODE_IPI_PL_1 = 66,
NODE_IPI_PL_2 = 67,
NODE_IPI_PL_3 = 68,
NODE_PL = 69,
NODE_GEM_TSU = 70,
NODE_SWDT_0 = 71,
NODE_SWDT_1 = 72,
NODE_CSU = 73,
NODE_PJTAG = 74,
NODE_TRACE = 75,
NODE_TESTSCAN = 76,
NODE_PMU = 77,
NODE_MAX = 78,
};
enum tap_delay_type {
PM_TAPDELAY_INPUT = 0,
PM_TAPDELAY_OUTPUT = 1,
};
enum dll_reset_type {
PM_DLL_RESET_ASSERT = 0,
PM_DLL_RESET_RELEASE = 1,
PM_DLL_RESET_PULSE = 2,
};
enum pm_query_id {
PM_QID_INVALID = 0,
PM_QID_CLOCK_GET_NAME = 1,
@ -215,6 +308,40 @@ enum zynqmp_pm_reset {
ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
};
enum pm_ioctl_id {
IOCTL_GET_RPU_OPER_MODE = 0,
IOCTL_SET_RPU_OPER_MODE = 1,
IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
IOCTL_TCM_COMB_CONFIG = 3,
IOCTL_SET_TAPDELAY_BYPASS = 4,
IOCTL_SET_SGMII_MODE = 5,
IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY = 7,
IOCTL_SET_PLL_FRAC_MODE = 8,
IOCTL_GET_PLL_FRAC_MODE = 9,
IOCTL_SET_PLL_FRAC_DATA = 10,
IOCTL_GET_PLL_FRAC_DATA = 11,
IOCTL_WRITE_GGS = 12,
IOCTL_READ_GGS = 13,
IOCTL_WRITE_PGGS = 14,
IOCTL_READ_PGGS = 15,
/* IOCTL for ULPI reset */
IOCTL_ULPI_RESET = 16,
/* Set healthy bit value*/
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
IOCTL_AFI = 18,
/* Probe counter read/write */
IOCTL_PROBE_COUNTER_READ = 19,
IOCTL_PROBE_COUNTER_WRITE = 20,
IOCTL_OSPI_MUX_SELECT = 21,
/* IOCTL for USB power request */
IOCTL_USB_SET_STATE = 22,
/* IOCTL to get last reset reason */
IOCTL_GET_LAST_RESET_REASON = 23,
/* AIE ISR Clear */
IOCTL_AIE_ISR_CLEAR = 24,
};
#define PM_SIP_SVC 0xc2000000
#define ZYNQMP_PM_VERSION_MAJOR 1