mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
42817eb85d
846 changed files with 13131 additions and 3408 deletions
|
@ -66,3 +66,4 @@ BSD 2-Clause License BSD-2-Clause Y bsd-2-clause.txt http://spdx.org/license
|
|||
BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http://spdx.org/licenses/BSD-3-Clause#licenseText
|
||||
IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt
|
||||
Boot Software) license
|
||||
ISC License ISC Y isc.txt https://spdx.org/licenses/ISC
|
||||
|
|
17
Licenses/isc.txt
Normal file
17
Licenses/isc.txt
Normal file
|
@ -0,0 +1,17 @@
|
|||
ISC License:
|
||||
Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC")
|
||||
Copyright (c) 1995-2003 by Internet Software Consortium
|
||||
|
||||
Permission to use, copy, modify, and/or distribute this software
|
||||
for any purpose with or without fee is hereby granted,
|
||||
provided that the above copyright notice and this permission notice
|
||||
appear in all copies.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES
|
||||
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE
|
||||
FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR
|
||||
ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
|
||||
WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
|
||||
ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
|
||||
THIS SOFTWARE.
|
4
Makefile
4
Makefile
|
@ -341,7 +341,7 @@ CHECK = sparse
|
|||
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
|
||||
-Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
|
||||
|
||||
KBUILD_CPPFLAGS := -D__KERNEL__
|
||||
KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
|
||||
|
||||
KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
|
||||
-Wno-format-security \
|
||||
|
@ -458,7 +458,7 @@ KBUILD_DEFCONFIG := sandbox_defconfig
|
|||
export KBUILD_DEFCONFIG KBUILD_KCONFIG
|
||||
|
||||
config: scripts_basic outputmakefile FORCE
|
||||
(Q)$(MAKE) $(build)=scripts/kconfig $@
|
||||
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
|
||||
|
||||
%config: scripts_basic outputmakefile FORCE
|
||||
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
|
||||
|
|
56
arch/Kconfig
56
arch/Kconfig
|
@ -49,6 +49,62 @@ config X86
|
|||
|
||||
endchoice
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
help
|
||||
This option should contain the architecture name to build the
|
||||
appropriate arch/<CONFIG_SYS_ARCH> directory.
|
||||
All the architectures should specify this option correctly.
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
help
|
||||
This option should contain the CPU name to build the correct
|
||||
arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
|
||||
|
||||
This is optional. For those targets without the CPU directory,
|
||||
leave this option empty.
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
help
|
||||
This option should contain the SoC name to build the directory
|
||||
arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
|
||||
|
||||
This is optional. For those targets without the SoC directory,
|
||||
leave this option empty.
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
help
|
||||
This option should contain the vendor name of the target board.
|
||||
If it is set and
|
||||
board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
|
||||
directory is compiled.
|
||||
If CONFIG_SYS_BOARD is also set, the sources under
|
||||
board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
|
||||
|
||||
This is optional. For those targets without the vendor directory,
|
||||
leave this option empty.
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
help
|
||||
This option should contain the name of the target board.
|
||||
If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
|
||||
or board/<CONFIG_SYS_BOARD> directory is compiled depending on
|
||||
whether CONFIG_SYS_VENDOR is set or not.
|
||||
|
||||
This is optional. For those targets without the board directory,
|
||||
leave this option empty.
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
help
|
||||
This option should contain the base name of board header file.
|
||||
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
|
||||
should be included from include/config.h.
|
||||
|
||||
source "arch/arc/Kconfig"
|
||||
source "arch/arm/Kconfig"
|
||||
source "arch/avr32/Kconfig"
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "ARC architecture"
|
|||
depends on ARC
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "arc"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,9 +2,11 @@ menu "ARM architecture"
|
|||
depends on ARM
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "arm"
|
||||
|
||||
config ARM64
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Target select"
|
||||
|
||||
|
@ -463,15 +465,21 @@ config TEGRA
|
|||
|
||||
config TARGET_VEXPRESS_AEMV8A
|
||||
bool "Support vexpress_aemv8a"
|
||||
|
||||
config TARGET_VEXPRESS_AEMV8A_SEMI
|
||||
bool "Support vexpress_aemv8a_semi"
|
||||
select ARM64
|
||||
|
||||
config TARGET_LS2085A_EMU
|
||||
bool "Support ls2085a_emu"
|
||||
select ARM64
|
||||
|
||||
config TARGET_LS2085A_SIMU
|
||||
bool "Support ls2085a_simu"
|
||||
select ARM64
|
||||
|
||||
config TARGET_LS1021AQDS
|
||||
bool "Support ls1021aqds_nor"
|
||||
|
||||
config TARGET_LS1021ATWR
|
||||
bool "Support ls1021atwr_nor"
|
||||
|
||||
config TARGET_BALLOON3
|
||||
bool "Support balloon3"
|
||||
|
@ -514,6 +522,8 @@ config TARGET_JORNADA
|
|||
|
||||
endchoice
|
||||
|
||||
source "arch/arm/cpu/armv8/Kconfig"
|
||||
|
||||
source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
|
||||
|
||||
source "arch/arm/cpu/armv7/exynos/Kconfig"
|
||||
|
@ -598,6 +608,8 @@ source "board/eukrea/cpu9260/Kconfig"
|
|||
source "board/eukrea/cpuat91/Kconfig"
|
||||
source "board/faraday/a320evb/Kconfig"
|
||||
source "board/freescale/ls2085a/Kconfig"
|
||||
source "board/freescale/ls1021aqds/Kconfig"
|
||||
source "board/freescale/ls1021atwr/Kconfig"
|
||||
source "board/freescale/mx23evk/Kconfig"
|
||||
source "board/freescale/mx25pdk/Kconfig"
|
||||
source "board/freescale/mx28evk/Kconfig"
|
||||
|
|
|
@ -54,11 +54,9 @@ config TARGET_CALIMAIN
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm926ejs"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "davinci"
|
||||
|
||||
source "board/enbw/enbw_cmc/Kconfig"
|
||||
|
|
|
@ -60,11 +60,9 @@ config TARGET_GOFLEXHOME
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm926ejs"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "kirkwood"
|
||||
|
||||
source "board/Marvell/openrd/Kconfig"
|
||||
|
|
|
@ -9,11 +9,9 @@ config NOMADIK_NHK8815
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm926ejs"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "nomadik"
|
||||
|
||||
source "board/st/nhk8815/Kconfig"
|
||||
|
|
|
@ -9,11 +9,9 @@ config TARGET_EDMINIV2
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm926ejs"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "orion5x"
|
||||
|
||||
source "board/LaCie/edminiv2/Kconfig"
|
||||
|
|
|
@ -1,23 +1,18 @@
|
|||
if ARCH_VERSATILE
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm926ejs"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "versatile"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "armltd"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "versatile"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "versatile"
|
||||
|
||||
endif
|
||||
|
|
|
@ -114,9 +114,25 @@ int at91_clock_init(unsigned long main_clock)
|
|||
void at91_periph_clk_enable(int id)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 regval;
|
||||
|
||||
if (id > 31)
|
||||
writel(1 << (id - 32), &pmc->pcer1);
|
||||
else
|
||||
writel(1 << id, &pmc->pcer);
|
||||
if (id > AT91_PMC_PCR_PID_MASK)
|
||||
return;
|
||||
|
||||
regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
|
||||
|
||||
writel(regval, &pmc->pcr);
|
||||
}
|
||||
|
||||
void at91_periph_clk_disable(int id)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 regval;
|
||||
|
||||
if (id > AT91_PMC_PCR_PID_MASK)
|
||||
return;
|
||||
|
||||
regval = AT91_PMC_PCR_CMD_WRITE | id;
|
||||
|
||||
writel(regval, &pmc->pcr);
|
||||
}
|
||||
|
|
|
@ -39,11 +39,9 @@ config TARGET_PEACH_PIT
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "exynos"
|
||||
|
||||
source "board/samsung/smdkv310/Kconfig"
|
||||
|
|
|
@ -1,19 +1,15 @@
|
|||
if ARCH_HIGHBANK
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "highbank"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "highbank"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "highbank"
|
||||
|
||||
endif
|
||||
|
|
|
@ -12,11 +12,9 @@ config TARGET_K2E_EVM
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "keystone"
|
||||
|
||||
source "board/ti/ks2_evm/Kconfig"
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
|
||||
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
||||
{
|
||||
|
@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void)
|
|||
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
|
||||
__raw_writel(tmp, KS2_DDR3APLLCTL1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
/**
|
||||
* ddr3_reset_workaround - reset workaround in case if leveling error
|
||||
* detected for PG 1.0 and 1.1 k2hk SoCs
|
||||
*/
|
||||
void ddr3_err_reset_workaround(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
unsigned int tmp_a;
|
||||
unsigned int tmp_b;
|
||||
|
||||
/*
|
||||
* Check for PGSR0 error bits of DDR3 PHY.
|
||||
* Check for WLERR, QSGERR, WLAERR,
|
||||
* RDERR, WDERR, REERR, WEERR error to see if they are set or not
|
||||
*/
|
||||
tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
|
||||
tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
|
||||
|
||||
if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
|
||||
printf("DDR Leveling Error Detected!\n");
|
||||
printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
|
||||
printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
|
||||
|
||||
/*
|
||||
* Write Keys to KICK registers to enable writes to registers
|
||||
* in boot config space
|
||||
*/
|
||||
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
|
||||
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
|
||||
|
||||
/*
|
||||
* Move DDR3A Module out of reset isolation by setting
|
||||
* MDCTL23[12] = 0
|
||||
*/
|
||||
tmp_a = __raw_readl(KS2_PSC_BASE +
|
||||
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
|
||||
|
||||
tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
|
||||
__raw_writel(tmp_a, KS2_PSC_BASE +
|
||||
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
|
||||
|
||||
/*
|
||||
* Move DDR3B Module out of reset isolation by setting
|
||||
* MDCTL24[12] = 0
|
||||
*/
|
||||
tmp_b = __raw_readl(KS2_PSC_BASE +
|
||||
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
|
||||
tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
|
||||
__raw_writel(tmp_b, KS2_PSC_BASE +
|
||||
PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
|
||||
|
||||
/*
|
||||
* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
|
||||
* to RSTCTRL and RSTCFG
|
||||
*/
|
||||
tmp = __raw_readl(KS2_RSTCTRL);
|
||||
tmp &= KS2_RSTCTRL_MASK;
|
||||
tmp |= KS2_RSTCTRL_KEY;
|
||||
__raw_writel(tmp, KS2_RSTCTRL);
|
||||
|
||||
/*
|
||||
* Set PLL Controller to drive hard reset on SW trigger by
|
||||
* setting RSTCFG[13] = 0
|
||||
*/
|
||||
tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
|
||||
tmp &= ~KS2_RSTYPE_PLL_SOFT;
|
||||
__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
|
||||
|
||||
reset_cpu(0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
12
arch/arm/cpu/armv7/ls102xa/Makefile
Normal file
12
arch/arm/cpu/armv7/ls102xa/Makefile
Normal file
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += clock.o
|
||||
obj-y += timer.o
|
||||
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
|
130
arch/arm/cpu/armv7/ls102xa/clock.c
Normal file
130
arch/arm/cpu/armv7/ls102xa/clock.c
Normal file
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <fsl_ifc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#endif
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
|
||||
u32 ccr;
|
||||
#endif
|
||||
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
|
||||
unsigned int cpu;
|
||||
const u8 core_cplx_pll[6] = {
|
||||
[0] = 0, /* CC1 PPL / 1 */
|
||||
[1] = 0, /* CC1 PPL / 2 */
|
||||
[4] = 1, /* CC2 PPL / 1 */
|
||||
[5] = 1, /* CC2 PPL / 2 */
|
||||
};
|
||||
|
||||
const u8 core_cplx_pll_div[6] = {
|
||||
[0] = 1, /* CC1 PPL / 1 */
|
||||
[1] = 2, /* CC1 PPL / 2 */
|
||||
[4] = 1, /* CC2 PPL / 1 */
|
||||
[5] = 2, /* CC2 PPL / 2 */
|
||||
};
|
||||
|
||||
uint i;
|
||||
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
||||
sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
|
||||
RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK;
|
||||
sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
|
||||
RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
|
||||
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
|
||||
if (ratio[i] > 4)
|
||||
freq_c_pll[i] = sysclk * ratio[i];
|
||||
else
|
||||
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
|
||||
}
|
||||
|
||||
for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
|
||||
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
|
||||
& 0xf;
|
||||
u32 cplx_pll = core_cplx_pll[c_pll_sel];
|
||||
|
||||
sys_info->freq_processor[cpu] =
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FSL_IFC)
|
||||
ccr = in_be32(&ifc_regs->ifc_ccr);
|
||||
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
|
||||
|
||||
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
|
||||
#endif
|
||||
}
|
||||
|
||||
int get_clocks(void)
|
||||
{
|
||||
struct sys_info sys_info;
|
||||
|
||||
get_sys_info(&sys_info);
|
||||
gd->cpu_clk = sys_info.freq_processor[0];
|
||||
gd->bus_clk = sys_info.freq_systembus;
|
||||
gd->mem_clk = sys_info.freq_ddrbus * 2;
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
gd->arch.sdhc_clk = gd->bus_clk;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
return gd->bus_clk;
|
||||
}
|
||||
|
||||
ulong get_ddr_freq(ulong dummy)
|
||||
{
|
||||
return gd->mem_clk;
|
||||
}
|
||||
|
||||
int get_serial_clock(void)
|
||||
{
|
||||
return gd->bus_clk / 2;
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_I2C_CLK:
|
||||
return get_bus_freq(0) / 2;
|
||||
case MXC_ESDHC_CLK:
|
||||
return get_bus_freq(0);
|
||||
case MXC_DSPI_CLK:
|
||||
return get_bus_freq(0) / 2;
|
||||
case MXC_UART_CLK:
|
||||
return get_bus_freq(0) / 2;
|
||||
default:
|
||||
printf("Unsupported clock\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
103
arch/arm/cpu/armv7/ls102xa/cpu.c
Normal file
103
arch/arm/cpu/armv7/ls102xa/cpu.c
Normal file
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <tsec.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_esdhc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char buf1[32], buf2[32];
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int svr, major, minor, ver, i;
|
||||
|
||||
svr = in_be32(&gur->svr);
|
||||
major = SVR_MAJ(svr);
|
||||
minor = SVR_MIN(svr);
|
||||
|
||||
puts("CPU: Freescale LayerScape ");
|
||||
|
||||
ver = SVR_SOC_VER(svr);
|
||||
switch (ver) {
|
||||
case SOC_VER_SLS1020:
|
||||
puts("SLS1020");
|
||||
break;
|
||||
case SOC_VER_LS1020:
|
||||
puts("LS1020");
|
||||
break;
|
||||
case SOC_VER_LS1021:
|
||||
puts("LS1021");
|
||||
break;
|
||||
case SOC_VER_LS1022:
|
||||
puts("LS1022");
|
||||
break;
|
||||
default:
|
||||
puts("Unknown");
|
||||
break;
|
||||
}
|
||||
|
||||
if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
|
||||
puts("E");
|
||||
|
||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
|
||||
|
||||
puts("Clock Configuration:");
|
||||
|
||||
printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
|
||||
printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
|
||||
printf("DDR:%-4s MHz (%s MT/s data rate), ",
|
||||
strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
|
||||
puts("\n");
|
||||
|
||||
/* Display the RCW, so that no one gets confused as to what RCW
|
||||
* we're actually using for this boot.
|
||||
*/
|
||||
puts("Reset Configuration Word (RCW):");
|
||||
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
||||
u32 rcw = in_be32(&gur->rcwsr[i]);
|
||||
|
||||
if ((i % 4) == 0)
|
||||
printf("\n %08x:", i * 4);
|
||||
printf(" %08x", rcw);
|
||||
}
|
||||
puts("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
#ifndef CONFIG_SYS_ICACHE_OFF
|
||||
icache_enable();
|
||||
#endif
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
dcache_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int cpu_mmc_init(bd_t *bis)
|
||||
{
|
||||
return fsl_esdhc_mmc_init(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
tsec_standard_init(bis);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
136
arch/arm/cpu/armv7/ls102xa/fdt.c
Normal file
136
arch/arm/cpu/armv7/ls102xa/fdt.c
Normal file
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <linux/ctype.h>
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
#include <tsec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void ft_fixup_enet_phy_connect_type(void *fdt)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
struct tsec_private *priv;
|
||||
const char *enet_path, *phy_path;
|
||||
char enet[16];
|
||||
char phy[16];
|
||||
int phy_node;
|
||||
int i = 0;
|
||||
int enet_id = 0;
|
||||
uint32_t ph;
|
||||
|
||||
while ((dev = eth_get_dev_by_index(i++)) != NULL) {
|
||||
if (strstr(dev->name, "eTSEC1"))
|
||||
enet_id = 0;
|
||||
else if (strstr(dev->name, "eTSEC2"))
|
||||
enet_id = 1;
|
||||
else if (strstr(dev->name, "eTSEC3"))
|
||||
enet_id = 2;
|
||||
else
|
||||
continue;
|
||||
|
||||
priv = dev->priv;
|
||||
if (priv->flags & TSEC_SGMII)
|
||||
continue;
|
||||
|
||||
sprintf(enet, "ethernet%d", enet_id);
|
||||
enet_path = fdt_get_alias(fdt, enet);
|
||||
if (!enet_path)
|
||||
continue;
|
||||
|
||||
sprintf(phy, "enet%d_rgmii_phy", enet_id);
|
||||
phy_path = fdt_get_alias(fdt, phy);
|
||||
if (!phy_path)
|
||||
continue;
|
||||
|
||||
phy_node = fdt_path_offset(fdt, phy_path);
|
||||
if (phy_node < 0)
|
||||
continue;
|
||||
|
||||
ph = fdt_create_phandle(fdt, phy_node);
|
||||
if (ph)
|
||||
do_fixup_by_path_u32(fdt, enet_path,
|
||||
"phy-handle", ph, 1);
|
||||
|
||||
do_fixup_by_path(fdt, enet_path, "phy-connection-type",
|
||||
phy_string_for_interface(
|
||||
PHY_INTERFACE_MODE_RGMII_ID),
|
||||
sizeof(phy_string_for_interface(
|
||||
PHY_INTERFACE_MODE_RGMII_ID)),
|
||||
1);
|
||||
}
|
||||
}
|
||||
|
||||
void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int off;
|
||||
int val;
|
||||
const char *sysclk_path;
|
||||
|
||||
unsigned long busclk = get_bus_freq(0);
|
||||
|
||||
fdt_fixup_ethernet(blob);
|
||||
|
||||
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
|
||||
while (off != -FDT_ERR_NOTFOUND) {
|
||||
val = gd->cpu_clk;
|
||||
fdt_setprop(blob, off, "clock-frequency", &val, 4);
|
||||
off = fdt_node_offset_by_prop_value(blob, off,
|
||||
"device_type", "cpu", 4);
|
||||
}
|
||||
|
||||
do_fixup_by_prop_u32(blob, "device_type", "soc",
|
||||
4, "bus-frequency", busclk / 2, 1);
|
||||
|
||||
ft_fixup_enet_phy_connect_type(blob);
|
||||
|
||||
#ifdef CONFIG_SYS_NS16550
|
||||
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
|
||||
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
|
||||
#endif
|
||||
|
||||
sysclk_path = fdt_get_alias(blob, "sysclk");
|
||||
if (sysclk_path)
|
||||
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
|
||||
CONFIG_SYS_CLK_FREQ, 1);
|
||||
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
|
||||
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
fdt_fixup_esdhc(blob, bd);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* platform bus clock = system bus clock/2
|
||||
* Here busclk = system bus clock
|
||||
* We are using the platform bus clock as 1588 Timer reference
|
||||
* clock source select
|
||||
*/
|
||||
do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
|
||||
"timer-frequency", busclk / 2, 1);
|
||||
|
||||
/*
|
||||
* clock-freq should change to clock-frequency and
|
||||
* flexcan-v1.0 should change to p1010-flexcan respectively
|
||||
* in the future.
|
||||
*/
|
||||
do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
|
||||
"clock_freq", busclk / 2, 1);
|
||||
|
||||
do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
|
||||
"clock-frequency", busclk / 2, 1);
|
||||
|
||||
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
|
||||
"clock-frequency", busclk / 2, 1);
|
||||
}
|
120
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
Normal file
120
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
Normal file
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include "fsl_ls1_serdes.h"
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
static u64 serdes1_prtcl_map;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
static u64 serdes2_prtcl_map;
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
u64 ret = 0;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
ret |= (1ULL << device) & serdes1_prtcl_map;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
ret |= (1ULL << device) & serdes2_prtcl_map;
|
||||
#endif
|
||||
|
||||
return !!ret;
|
||||
}
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = in_be32(&gur->rcwsr[4]);
|
||||
int i;
|
||||
|
||||
switch (sd) {
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
case FSL_SRDS_1:
|
||||
cfg &= RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
case FSL_SRDS_2:
|
||||
cfg &= RCWSR4_SRDS2_PRTCL_MASK;
|
||||
cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("invalid SerDes%d\n", sd);
|
||||
break;
|
||||
}
|
||||
/* Is serdes enabled at all? */
|
||||
if (unlikely(cfg == 0))
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (serdes_get_prtcl(sd, cfg, i) == device)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u64 serdes_prtcl_map = 0;
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
|
||||
cfg >>= sd_prctl_shift;
|
||||
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
|
||||
|
||||
if (!is_serdes_prtcl_valid(sd, cfg))
|
||||
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
|
||||
|
||||
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
|
||||
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
|
||||
|
||||
serdes_prtcl_map |= (1ULL << lane_prtcl);
|
||||
}
|
||||
|
||||
return serdes_prtcl_map;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
RCWSR4_SRDS1_PRTCL_MASK,
|
||||
RCWSR4_SRDS1_PRTCL_SHIFT);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR +
|
||||
FSL_SRDS_2 * 0x1000,
|
||||
RCWSR4_SRDS2_PRTCL_MASK,
|
||||
RCWSR4_SRDS2_PRTCL_SHIFT);
|
||||
#endif
|
||||
}
|
||||
|
||||
const char *serdes_clock_to_string(u32 clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case SRDS_PLLCR0_RFCK_SEL_100:
|
||||
return "100";
|
||||
case SRDS_PLLCR0_RFCK_SEL_125:
|
||||
return "125";
|
||||
default:
|
||||
return "100";
|
||||
}
|
||||
}
|
12
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
Normal file
12
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_LS1_SERDES_H
|
||||
#define __FSL_LS1_SERDES_H
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
int serdes_lane_enabled(int lane);
|
||||
#endif /* __FSL_LS1_SERDES_H */
|
41
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
Normal file
41
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
Normal file
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
|
||||
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
|
||||
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
||||
[0x10] = {PCIE1, SATA1, PCIE2, PCIE2},
|
||||
[0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2},
|
||||
[0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2},
|
||||
[0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2},
|
||||
[0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2},
|
||||
[0x80] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
return serdes_cfg_tbl[cfg][lane];
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (serdes_cfg_tbl[prtcl][i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
127
arch/arm/cpu/armv7/ls102xa/timer.c
Normal file
127
arch/arm/cpu/armv7/ls102xa/timer.c
Normal file
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* This function is intended for SHORT delays only.
|
||||
* It will overflow at around 10 seconds @ 400MHz,
|
||||
* or 20 seconds @ 200MHz.
|
||||
*/
|
||||
unsigned long usec2ticks(unsigned long usec)
|
||||
{
|
||||
ulong ticks;
|
||||
|
||||
if (usec < 1000)
|
||||
ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
|
||||
else
|
||||
ticks = ((usec / 10) * (get_tbclk() / 100000));
|
||||
|
||||
return ticks;
|
||||
}
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, freq);
|
||||
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long usec)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
usec = usec * freq + 999999;
|
||||
do_div(usec, 1000000);
|
||||
|
||||
return usec;
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
|
||||
unsigned long ctrl, val, freq;
|
||||
|
||||
/* Enable System Counter */
|
||||
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
|
||||
|
||||
freq = GENERIC_TIMER_CLK;
|
||||
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
|
||||
/* Set PL1 Physical Timer Ctrl */
|
||||
ctrl = ARCH_TIMER_CTRL_ENABLE;
|
||||
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
|
||||
|
||||
/* Set PL1 Physical Comp Value */
|
||||
val = TIMER_COMP_VAL;
|
||||
asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
|
||||
|
||||
gd->arch.tbl = 0;
|
||||
gd->arch.tbu = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
unsigned long long now;
|
||||
|
||||
asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
|
||||
|
||||
gd->arch.tbl = (unsigned long)(now & 0xffffffff);
|
||||
gd->arch.tbu = (unsigned long)(now >> 32);
|
||||
|
||||
return now;
|
||||
}
|
||||
|
||||
unsigned long get_timer_masked(void)
|
||||
{
|
||||
return tick_to_time(get_ticks());
|
||||
}
|
||||
|
||||
unsigned long get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
/* delay x useconds and preserve advance timstamp value */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long start;
|
||||
unsigned long tmo;
|
||||
|
||||
start = get_ticks(); /* get current timestamp */
|
||||
tmo = us_to_tick(usec); /* convert usecs to ticks */
|
||||
|
||||
while ((get_ticks() - start) < tmo)
|
||||
; /* loop till time has passed */
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
return freq;
|
||||
}
|
|
@ -75,11 +75,9 @@ config TARGET_TWISTER
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "omap3"
|
||||
|
||||
source "board/logicpd/am3517evm/Kconfig"
|
||||
|
|
|
@ -15,11 +15,9 @@ config TARGET_OMAP4_SDP4430
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "omap4"
|
||||
|
||||
source "board/gumstix/duovero/Kconfig"
|
||||
|
|
|
@ -15,11 +15,9 @@ config TARGET_DRA7XX_EVM
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "omap5"
|
||||
|
||||
source "board/compulab/cm_t54/Kconfig"
|
||||
|
|
|
@ -21,11 +21,9 @@ config TARGET_ALT
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "rmobile"
|
||||
|
||||
source "board/atmark-techno/armadillo-800eva/Kconfig"
|
||||
|
|
|
@ -18,7 +18,6 @@ config TEGRA124
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "arm720t" if SPL_BUILD
|
||||
default "armv7" if !SPL_BUILD
|
||||
|
||||
|
|
|
@ -9,7 +9,6 @@ config TARGET_DALMORE
|
|||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "tegra114"
|
||||
|
||||
source "board/nvidia/dalmore/Kconfig"
|
||||
|
|
|
@ -12,7 +12,6 @@ config TARGET_VENICE2
|
|||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "tegra124"
|
||||
|
||||
source "board/nvidia/jetson-tk1/Kconfig"
|
||||
|
|
|
@ -36,7 +36,6 @@ config TARGET_COLIBRI_T20_IRIS
|
|||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "tegra20"
|
||||
|
||||
source "board/nvidia/harmony/Kconfig"
|
||||
|
|
|
@ -18,7 +18,6 @@ config TARGET_TEC_NG
|
|||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "tegra30"
|
||||
|
||||
source "board/nvidia/beaver/Kconfig"
|
||||
|
|
|
@ -18,23 +18,18 @@ config TARGET_ZYNQ_ZC770
|
|||
endchoice
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "zynq"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "xilinx"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "zynq"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "zynq_zed" if TARGET_ZYNQ_ZED
|
||||
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
|
||||
default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
|
||||
|
|
6
arch/arm/cpu/armv8/Kconfig
Normal file
6
arch/arm/cpu/armv8/Kconfig
Normal file
|
@ -0,0 +1,6 @@
|
|||
if ARM64
|
||||
|
||||
config SYS_CPU
|
||||
default "armv8"
|
||||
|
||||
endif
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Dalmore";
|
||||
compatible = "nvidia,dalmore", "nvidia,tegra114";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
i2c1 = "/i2c@7000c000";
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
#include <dt-bindings/clock/tegra114-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
|
@ -116,6 +117,58 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_UARTA>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_UARTB>;
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_UARTC>;
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA114_CLK_UARTD>;
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra114-spi";
|
||||
reg = <0x7000d400 0x200>;
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Jetson TK1";
|
||||
compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
i2c1 = "/i2c@7000c000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Venice2";
|
||||
compatible = "nvidia,venice2", "nvidia,tegra124";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
i2c1 = "/i2c@7000c000";
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
|
@ -126,6 +127,71 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTA>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTB>;
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTC>;
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTD>;
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uarte: serial@70006400 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006400 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000d400 0x200>;
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Toradex Colibri T20";
|
||||
compatible = "toradex,t20", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5000000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Tegra20 Harmony evaluation board";
|
||||
compatible = "nvidia,harmony", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5004000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Avionic Design Medcom-Wide";
|
||||
compatible = "ad,medcom-wide", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
sdhci0 = "/sdhci@c8000600";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Toshiba AC100 / Dynabook AZ";
|
||||
compatible = "compal,paz00", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
sdhci0 = "/sdhci@c8000600";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Avionic Design Plutux";
|
||||
compatible = "ad,plutux", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
sdhci0 = "/sdhci@c8000600";
|
||||
|
|
|
@ -10,6 +10,10 @@
|
|||
bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* This defines the order of our ports */
|
||||
usb0 = "/usb@c5008000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Avionic Design Tamonten Evaluation Carrier";
|
||||
compatible = "ad,tec", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
sdhci0 = "/sdhci@c8000600";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "Compulab TrimSlice board";
|
||||
compatible = "compulab,trimslice", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5000000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Tegra20 Ventana evaluation board";
|
||||
compatible = "nvidia,ventana", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
sdhci0 = "/sdhci@c8000600";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Tegra20 Whistler evaluation board";
|
||||
compatible = "nvidia,whistler", "nvidia,tegra20";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
usb0 = "/usb@c5008000";
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
|
@ -189,39 +190,69 @@
|
|||
dma-channel = < 1 >;
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = < 68 >;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_UARTA>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = < 69 >;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_UARTB>;
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = < 78 >;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_UARTC>;
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = < 122 >;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_UARTD>;
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@70006400 {
|
||||
uarte: serial@70006400 {
|
||||
compatible = "nvidia,tegra20-uart";
|
||||
reg = <0x70006400 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = < 123 >;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@70008000 {
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Beaver";
|
||||
compatible = "nvidia,beaver", "nvidia,tegra30";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
i2c1 = "/i2c@7000c000";
|
||||
|
|
|
@ -6,6 +6,10 @@
|
|||
model = "NVIDIA Cardhu";
|
||||
compatible = "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uarta;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
i2c1 = "/i2c@7000c000";
|
||||
|
|
|
@ -8,6 +8,10 @@
|
|||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uartd;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000c000";
|
||||
i2c1 = "/i2c@7000c700";
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
#include <dt-bindings/clock/tegra30-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
|
@ -122,6 +123,71 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uarta: serial@70006000 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_UARTA>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartb: serial@70006040 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_UARTB>;
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@70006200 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_UARTC>;
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartd: serial@70006300 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_UARTD>;
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uarte: serial@70006400 {
|
||||
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x70006400 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d400 0x200>;
|
||||
|
|
|
@ -54,7 +54,7 @@ typedef struct at91_pmc {
|
|||
u32 reserved5[21];
|
||||
u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
|
||||
u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
|
||||
#ifdef CONFIG_SAMA5D3
|
||||
#ifdef CPU_HAS_PCR
|
||||
u32 reserved6[8];
|
||||
u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
|
||||
u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
|
||||
|
@ -147,6 +147,10 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_IXR_PCKRDY3 0x00000800
|
||||
#define AT91_PMC_IXR_MOSCSELS 0x00010000
|
||||
|
||||
#define AT91_PMC_PCR_PID_MASK (0x3f)
|
||||
#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
|
||||
#define AT91_PMC_PCR_EN (0x1 << 28)
|
||||
|
||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||
|
|
|
@ -80,4 +80,5 @@ static inline unsigned long get_mci_clk_rate(void)
|
|||
|
||||
int at91_clock_init(unsigned long main_clock);
|
||||
void at91_periph_clk_enable(int id);
|
||||
void at91_periph_clk_disable(int id);
|
||||
#endif /* __ASM_ARM_ARCH_CLK_H__ */
|
||||
|
|
|
@ -188,6 +188,7 @@
|
|||
#define ATMEL_PIO_PORTS 5
|
||||
#define CPU_HAS_PIO3
|
||||
#define PIO_SCDR_DIV 0x3fff
|
||||
#define CPU_HAS_PCR
|
||||
|
||||
/*
|
||||
* PMECC table in ROM
|
||||
|
|
|
@ -14,7 +14,8 @@
|
|||
#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
|
||||
#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
|
||||
#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
|
||||
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
|
||||
#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
|
||||
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
|
||||
#else
|
||||
struct at91_cs {
|
||||
u32 setup; /* 0x600 SMC Setup Register */
|
||||
|
|
|
@ -50,6 +50,7 @@ struct ddr3_emif_config {
|
|||
|
||||
void ddr3_init(void);
|
||||
void ddr3_reset_ddrphy(void);
|
||||
void ddr3_err_reset_workaround(void);
|
||||
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
|
||||
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
|
||||
|
||||
|
|
|
@ -121,9 +121,11 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
|
||||
#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
|
||||
#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
|
||||
#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
|
||||
#define KS2_RSTCTRL_KEY 0x5a69
|
||||
#define KS2_RSTCTRL_MASK 0xffff0000
|
||||
#define KS2_RSTCTRL_SWRST 0xfffe0000
|
||||
#define KS2_RSTYPE_PLL_SOFT BIT(13)
|
||||
|
||||
/* SPI */
|
||||
#define KS2_SPI0_BASE 0x21000400
|
||||
|
|
23
arch/arm/include/asm/arch-ls102xa/clock.h
Normal file
23
arch/arm/include/asm/arch-ls102xa/clock.h
Normal file
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
#define __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_DSPI_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
|
78
arch/arm/include/asm/arch-ls102xa/config.h
Normal file
78
arch/arm/include/asm/arch-ls102xa/config.h
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
|
||||
#define _ASM_ARMV7_LS102XA_CONFIG_
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#define OCRAM_BASE_ADDR 0x10000000
|
||||
#define OCRAM_SIZE 0x00020000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
|
||||
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
|
||||
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
|
||||
|
||||
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
|
||||
|
||||
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#ifdef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
#define CONFIG_SYS_FSL_DCU_BE
|
||||
|
||||
#define DCU_LAYER_MAX_NUM 16
|
||||
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
||||
#ifdef CONFIG_LS102XA
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
|
33
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
Normal file
33
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
Normal file
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
SATA1,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
493
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
Normal file
493
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
Normal file
|
@ -0,0 +1,493 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
#define __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
|
||||
#define IS_E_PROCESSOR(svr) (svr & 0x80000)
|
||||
|
||||
#define SOC_VER_SLS1020 0x00
|
||||
#define SOC_VER_LS1020 0x10
|
||||
#define SOC_VER_LS1021 0x11
|
||||
#define SOC_VER_LS1022 0x12
|
||||
|
||||
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
|
||||
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
|
||||
|
||||
#define TIMER_COMP_VAL 0xffffffff
|
||||
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
|
||||
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
};
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u8 res_084[0x94-0x84];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa4-0x9c];
|
||||
u32 svr; /* System version */
|
||||
u8 res_0a8[0xb0-0xa8];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr;
|
||||
u8 res_404[0x550-0x404];
|
||||
u32 sataliodnr;
|
||||
u8 res_554[0x604-0x554];
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
u8 res_60c[0x740-0x60c]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[1]; /* Core Cluster n Topology Register */
|
||||
u8 res_848[0xe60-0x848];
|
||||
u32 ddrclkdr;
|
||||
u8 res_e60[0xe68-0xe64];
|
||||
u32 ifcclkdr;
|
||||
u8 res_e68[0xe80-0xe6c];
|
||||
u32 sdhcpcr;
|
||||
};
|
||||
|
||||
#define SCFG_SCFGREVCR_REV 0xffffffff
|
||||
#define SCFG_SCFGREVCR_NOREV 0
|
||||
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
|
||||
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
|
||||
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr;
|
||||
u32 resv0[2];
|
||||
u32 etsecclkdpslpcr;
|
||||
u32 resv1[5];
|
||||
u32 fuseovrdcr;
|
||||
u32 pixclkcr;
|
||||
u32 resv2[5];
|
||||
u32 spimsicr;
|
||||
u32 resv3[6];
|
||||
u32 pex1pmwrcr;
|
||||
u32 pex1pmrdsr;
|
||||
u32 resv4[3];
|
||||
u32 usb3prm1cr;
|
||||
u32 usb4prm2cr;
|
||||
u32 pex1rdmsgpldlsbsr;
|
||||
u32 pex1rdmsgpldmsbsr;
|
||||
u32 pex2rdmsgpldlsbsr;
|
||||
u32 pex2rdmsgpldmsbsr;
|
||||
u32 pex1rdmmsgrqsr;
|
||||
u32 pex2rdmmsgrqsr;
|
||||
u32 spimsiclrcr;
|
||||
u32 pex1mscportsr;
|
||||
u32 pex2mscportsr;
|
||||
u32 pex2pmwrcr;
|
||||
u32 resv5[24];
|
||||
u32 mac1_streamid;
|
||||
u32 mac2_streamid;
|
||||
u32 mac3_streamid;
|
||||
u32 pex1_streamid;
|
||||
u32 pex2_streamid;
|
||||
u32 dma_streamid;
|
||||
u32 sata_streamid;
|
||||
u32 usb3_streamid;
|
||||
u32 qe_streamid;
|
||||
u32 sdhc_streamid;
|
||||
u32 adma_streamid;
|
||||
u32 letechsftrstcr;
|
||||
u32 core0_sft_rst;
|
||||
u32 core1_sft_rst;
|
||||
u32 resv6[1];
|
||||
u32 usb_hi_addr;
|
||||
u32 etsecclkadjcr;
|
||||
u32 sai_clk;
|
||||
u32 resv7[1];
|
||||
u32 dcu_streamid;
|
||||
u32 usb2_streamid;
|
||||
u32 ftm_reset;
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u32 pmcintecr;
|
||||
u32 pmcintlecr;
|
||||
u32 pmcintsr;
|
||||
u32 qos1;
|
||||
u32 qos2;
|
||||
u32 qos3;
|
||||
u32 cci_cfg;
|
||||
u32 resv8[1];
|
||||
u32 etsecdmamcr;
|
||||
u32 usb3prm3cr;
|
||||
u32 resv9[1];
|
||||
u32 debug_streamid;
|
||||
u32 resv10[5];
|
||||
u32 snpcnfgcr;
|
||||
u32 resv11[1];
|
||||
u32 intpcr;
|
||||
u32 resv12[20];
|
||||
u32 scfgrevcr;
|
||||
u32 coresrencr;
|
||||
u32 pex2pmrdsr;
|
||||
u32 ddrc1cr;
|
||||
u32 ddrc2cr;
|
||||
u32 ddrc3cr;
|
||||
u32 ddrc4cr;
|
||||
u32 ddrgcr;
|
||||
u32 resv13[120];
|
||||
u32 qeioclkcr;
|
||||
u32 etsecmcr;
|
||||
u32 sdhciovserlcr;
|
||||
u32 resv14[61];
|
||||
u32 sparecr;
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x1c];
|
||||
} clkcsr[2];
|
||||
u8 res_040[0x7c0]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define MAX_SERDES 1
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define SRDS_MAX_BANK 2
|
||||
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u8 res_18[0x20-0x18];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0xe0-0xb4];
|
||||
u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
|
||||
u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
|
||||
u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
|
||||
u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
|
||||
u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
|
||||
u8 res_f4[0x100-0xf4];
|
||||
struct {
|
||||
u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} srdslnpssr[4];
|
||||
u8 res_180[0x300-0x180];
|
||||
u32 srdspexeqcr;
|
||||
u32 srdspexeqpcr[11];
|
||||
u8 res_330[0x400-0x330];
|
||||
u32 srdspexapcr;
|
||||
u8 res_404[0x440-0x404];
|
||||
u32 srdspexbpcr;
|
||||
u8 res_444[0x800-0x444];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D, E, F, G, H */
|
||||
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
|
||||
};
|
||||
|
||||
#define DDR_SDRAM_CFG 0x470c0008
|
||||
#define DDR_CS0_BNDS 0x008000bf
|
||||
#define DDR_CS0_CONFIG 0x80014302
|
||||
#define DDR_TIMING_CFG_0 0x50550004
|
||||
#define DDR_TIMING_CFG_1 0xbcb38c56
|
||||
#define DDR_TIMING_CFG_2 0x0040d120
|
||||
#define DDR_TIMING_CFG_3 0x010e1000
|
||||
#define DDR_TIMING_CFG_4 0x00000001
|
||||
#define DDR_TIMING_CFG_5 0x03401400
|
||||
#define DDR_SDRAM_CFG_2 0x00401010
|
||||
#define DDR_SDRAM_MODE 0x00061c60
|
||||
#define DDR_SDRAM_MODE_2 0x00180000
|
||||
#define DDR_SDRAM_INTERVAL 0x18600618
|
||||
#define DDR_DDR_WRLVL_CNTL 0x8655f605
|
||||
#define DDR_DDR_WRLVL_CNTL_2 0x05060607
|
||||
#define DDR_DDR_WRLVL_CNTL_3 0x05050505
|
||||
#define DDR_DDR_CDR1 0x80040000
|
||||
#define DDR_DDR_CDR2 0x00000001
|
||||
#define DDR_SDRAM_CLK_CNTL 0x02000000
|
||||
#define DDR_DDR_ZQ_CNTL 0x89080600
|
||||
#define DDR_CS0_CONFIG_2 0
|
||||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000
|
||||
|
||||
/* DDR memory controller registers */
|
||||
struct ccsr_ddr {
|
||||
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
|
||||
u32 resv1[1];
|
||||
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
|
||||
u32 resv2[1];
|
||||
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
|
||||
u32 resv3[1];
|
||||
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
|
||||
u32 resv4[25];
|
||||
u32 cs0_config; /* Chip Select Configuration */
|
||||
u32 cs1_config; /* Chip Select Configuration */
|
||||
u32 cs2_config; /* Chip Select Configuration */
|
||||
u32 cs3_config; /* Chip Select Configuration */
|
||||
u32 resv5[12];
|
||||
u32 cs0_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs1_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs2_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs3_config_2; /* Chip Select Configuration 2 */
|
||||
u32 resv6[12];
|
||||
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
|
||||
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
|
||||
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
|
||||
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
|
||||
u32 sdram_cfg; /* SDRAM Control Configuration */
|
||||
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
|
||||
u32 sdram_mode; /* SDRAM Mode Configuration */
|
||||
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
|
||||
u32 sdram_md_cntl; /* SDRAM Mode Control */
|
||||
u32 sdram_interval; /* SDRAM Interval Configuration */
|
||||
u32 sdram_data_init; /* SDRAM Data initialization */
|
||||
u32 resv7[1];
|
||||
u32 sdram_clk_cntl; /* SDRAM Clock Control */
|
||||
u32 resv8[5];
|
||||
u32 init_addr; /* training init addr */
|
||||
u32 init_ext_addr; /* training init extended addr */
|
||||
u32 resv9[4];
|
||||
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
|
||||
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
|
||||
u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
|
||||
u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
|
||||
u32 ddr_zq_cntl; /* ZQ calibration control*/
|
||||
u32 ddr_wrlvl_cntl; /* write leveling control*/
|
||||
u32 resv10[1];
|
||||
u32 ddr_sr_cntr; /* self refresvh counter */
|
||||
u32 ddr_sdram_rcw_1; /* Control Words 1 */
|
||||
u32 ddr_sdram_rcw_2; /* Control Words 2 */
|
||||
u32 resv11[2];
|
||||
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
|
||||
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
|
||||
u32 resv12[2];
|
||||
u32 ddr_sdram_rcw_3; /* Control Words 3 */
|
||||
u32 ddr_sdram_rcw_4; /* Control Words 4 */
|
||||
u32 ddr_sdram_rcw_5; /* Control Words 5 */
|
||||
u32 ddr_sdram_rcw_6; /* Control Words 6 */
|
||||
u32 resv13[20];
|
||||
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
|
||||
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
|
||||
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
|
||||
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
|
||||
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
|
||||
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
|
||||
u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
|
||||
u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
|
||||
u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
|
||||
u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
|
||||
u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
|
||||
u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
|
||||
u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
|
||||
u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
|
||||
u32 resv14[4];
|
||||
u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
|
||||
u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
|
||||
u32 resv15[2];
|
||||
u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */
|
||||
u32 resv16[15];
|
||||
u32 deskew_cntl; /* SDRAM Deskew Control */
|
||||
u32 resv17[545];
|
||||
u32 ddr_dsr1; /* Debug Status 1 */
|
||||
u32 ddr_dsr2; /* Debug Status 2 */
|
||||
u32 ddr_cdr1; /* Control Driver 1 */
|
||||
u32 ddr_cdr2; /* Control Driver 2 */
|
||||
u32 resv18[50];
|
||||
u32 ip_rev1; /* IP Block Revision 1 */
|
||||
u32 ip_rev2; /* IP Block Revision 2 */
|
||||
u32 eor; /* Enhanced Optimization Register */
|
||||
u32 resv19[63];
|
||||
u32 mtcr; /* Memory Test Control Register */
|
||||
u32 resv20[7];
|
||||
u32 mtp1; /* Memory Test Pattern 1 */
|
||||
u32 mtp2; /* Memory Test Pattern 2 */
|
||||
u32 mtp3; /* Memory Test Pattern 3 */
|
||||
u32 mtp4; /* Memory Test Pattern 4 */
|
||||
u32 mtp5; /* Memory Test Pattern 5 */
|
||||
u32 mtp6; /* Memory Test Pattern 6 */
|
||||
u32 mtp7; /* Memory Test Pattern 7 */
|
||||
u32 mtp8; /* Memory Test Pattern 8 */
|
||||
u32 mtp9; /* Memory Test Pattern 9 */
|
||||
u32 mtp10; /* Memory Test Pattern 10 */
|
||||
u32 resv21[6];
|
||||
u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */
|
||||
u32 ddr_mt_st_addr; /* Memory Test Start Address */
|
||||
u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */
|
||||
u32 ddr_mt_end_addr; /* Memory Test End Address */
|
||||
u32 resv22[36];
|
||||
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
|
||||
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
|
||||
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
|
||||
u32 resv23[5];
|
||||
u32 capture_data_hi; /* Data Path Read Capture High */
|
||||
u32 capture_data_lo; /* Data Path Read Capture Low */
|
||||
u32 capture_ecc; /* Data Path Read Capture ECC */
|
||||
u32 resv24[5];
|
||||
u32 err_detect; /* Error Detect */
|
||||
u32 err_disable; /* Error Disable */
|
||||
u32 err_int_en;
|
||||
u32 capture_attributes; /* Error Attrs Capture */
|
||||
u32 capture_address; /* Error Addr Capture */
|
||||
u32 capture_ext_address; /* Error Extended Addr Capture */
|
||||
u32 err_sbe; /* Single-Bit ECC Error Management */
|
||||
u32 resv25[105];
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
|
53
arch/arm/include/asm/arch-ls102xa/imx-regs.h
Normal file
53
arch/arm/include/asm/arch-ls102xa/imx-regs.h
Normal file
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX_REGS_H__
|
||||
#define __ASM_ARCH_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef _TEGRA_GPIO_H_
|
||||
#define _TEGRA_GPIO_H_
|
||||
|
||||
#define TEGRA_GPIOS_PER_PORT 8
|
||||
#define TEGRA_PORTS_PER_BANK 4
|
||||
#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
|
||||
#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
|
||||
|
||||
|
@ -25,9 +27,14 @@ struct tegra_gpio_config {
|
|||
u32 init:2;
|
||||
};
|
||||
|
||||
/*
|
||||
* Tegra-specific GPIO API
|
||||
/**
|
||||
* tegra_spl_gpio_direction_output() - set the output value of a GPIO
|
||||
*
|
||||
* This function is only used from SPL on seaboard, which needs to enable a
|
||||
* GPIO to get the UART running. It could be done in U-Boot rather than SPL,
|
||||
* but for now, this gets it working
|
||||
*/
|
||||
int tegra_spl_gpio_direction_output(int gpio, int value);
|
||||
|
||||
/**
|
||||
* Configure a list of GPIOs
|
||||
|
@ -37,8 +44,4 @@ struct tegra_gpio_config {
|
|||
*/
|
||||
void gpio_config_table(const struct tegra_gpio_config *config, int len);
|
||||
|
||||
void gpio_info(void);
|
||||
|
||||
#define gpio_status() gpio_info()
|
||||
|
||||
#endif /* TEGRA_GPIO_H_ */
|
||||
|
|
|
@ -23,4 +23,8 @@
|
|||
#include <asm/arch-fsl-lsch3/config.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LS102XA
|
||||
#include <asm/arch/config.h>
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -376,7 +376,12 @@ out:
|
|||
return retval;
|
||||
}
|
||||
|
||||
#elif !defined(readb)
|
||||
#else
|
||||
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
|
||||
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
|
||||
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
|
||||
|
||||
#if !defined(readb)
|
||||
|
||||
#define readb(addr) (__readwrite_bug("readb"),0)
|
||||
#define readw(addr) (__readwrite_bug("readw"),0)
|
||||
|
@ -389,6 +394,7 @@ out:
|
|||
|
||||
#define check_signature(io,sig,len) (0)
|
||||
|
||||
#endif
|
||||
#endif /* __mem_pci */
|
||||
|
||||
/*
|
||||
|
|
|
@ -28,6 +28,9 @@ void __weak board_init_f(ulong dummy)
|
|||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* Set global data pointer. */
|
||||
gd = &gdata;
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "AVR32 architecture"
|
|||
depends on AVR32
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "avr32"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "Blackfin architecture"
|
|||
depends on BLACKFIN
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "blackfin"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "M68000 architecture"
|
|||
depends on M68K
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "m68k"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "MicroBlaze architecture"
|
|||
depends on MICROBLAZE
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "microblaze"
|
||||
|
||||
choice
|
||||
|
|
|
@ -27,7 +27,11 @@ typedef int __kernel_pid_t;
|
|||
typedef unsigned short __kernel_ipc_pid_t;
|
||||
typedef unsigned int __kernel_uid_t;
|
||||
typedef unsigned int __kernel_gid_t;
|
||||
#ifdef __GNUC__
|
||||
typedef __SIZE_TYPE__ __kernel_size_t;
|
||||
#else
|
||||
typedef unsigned int __kernel_size_t;
|
||||
#endif
|
||||
typedef int __kernel_ssize_t;
|
||||
typedef int __kernel_ptrdiff_t;
|
||||
typedef long __kernel_time_t;
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "MIPS architecture"
|
|||
depends on MIPS
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "mips"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "NDS32 architecture"
|
|||
depends on NDS32
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "nds32"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "Nios II architecture"
|
|||
depends on NIOS2
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "nios2"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "OpenRISC architecture"
|
|||
depends on OPENRISC
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "openrisc"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "PowerPC architecture"
|
|||
depends on PPC
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "powerpc"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "74xx_7xx CPU"
|
|||
depends on 74xx_7xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "74xx_7xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc512x CPU"
|
|||
depends on MPC512X
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc512x"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc5xx CPU"
|
|||
depends on 5xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc5xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc5xxx CPU"
|
|||
depends on MPC5xxx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc5xxx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc824x CPU"
|
|||
depends on MPC824X
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc824x"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc8260 CPU"
|
|||
depends on MPC8260
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc8260"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc83xx CPU"
|
|||
depends on MPC83xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc83xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc85xx CPU"
|
|||
depends on MPC85xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc85xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc86xx CPU"
|
|||
depends on MPC86xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc86xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "mpc8xx CPU"
|
|||
depends on 8xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "mpc8xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "ppc4xx CPU"
|
|||
depends on 4xx
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "ppc4xx"
|
||||
|
||||
choice
|
||||
|
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PPC_FSL_ENET_H
|
||||
#define __ASM_PPC_FSL_ENET_H
|
||||
|
||||
#include <phy.h>
|
||||
|
||||
struct tsec_mii_mng {
|
||||
u32 miimcfg; /* MII management configuration reg */
|
||||
u32 miimcom; /* MII management command reg */
|
||||
u32 miimadd; /* MII management address reg */
|
||||
u32 miimcon; /* MII management control reg */
|
||||
u32 miimstat; /* MII management status reg */
|
||||
u32 miimind; /* MII management indication reg */
|
||||
u32 ifstat; /* Interface Status Register */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
|
||||
|
||||
#endif /* __ASM_PPC_FSL_ENET_H */
|
|
@ -2,15 +2,12 @@ menu "Sandbox architecture"
|
|||
depends on SANDBOX
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "sandbox"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "sandbox"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "sandbox"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -1,6 +1,16 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "/serial";
|
||||
};
|
||||
|
||||
/* Needs to be available prior to relocation */
|
||||
uart0: serial {
|
||||
compatible = "sandbox,serial";
|
||||
sandbox,text-colour = "cyan";
|
||||
};
|
||||
|
||||
triangle {
|
||||
compatible = "demo-shape";
|
||||
colour = "cyan";
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "SuperH architecture"
|
|||
depends on SH
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "sh"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "SPARC architecture"
|
|||
depends on SPARC
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "sparc"
|
||||
|
||||
choice
|
||||
|
|
|
@ -2,7 +2,6 @@ menu "x86 architecture"
|
|||
depends on X86
|
||||
|
||||
config SYS_ARCH
|
||||
string
|
||||
default "x86"
|
||||
|
||||
choice
|
||||
|
|
|
@ -1,15 +1,12 @@
|
|||
if TARGET_ECO5PK
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "eco5pk"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "8dtech"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "eco5pk"
|
||||
|
||||
endif
|
||||
|
|
|
@ -1,23 +1,18 @@
|
|||
if TARGET_ADP_AG101
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "n1213"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "adp-ag101"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "AndesTech"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "ag101"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "adp-ag101"
|
||||
|
||||
endif
|
||||
|
|
|
@ -1,23 +1,18 @@
|
|||
if TARGET_ADP_AG101P
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "n1213"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "adp-ag101p"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "AndesTech"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "ag101"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "adp-ag101p"
|
||||
|
||||
endif
|
||||
|
|
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Reference in a new issue