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arm64: zynqmp: Rename zc1275 to zcu1275

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Name of this platform has changed and released to customers that's why
name has also changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: uboot
This commit is contained in:
Michal Simek 2019-05-21 12:07:23 +02:00
parent ce7b93d4fc
commit 420d446781
5 changed files with 12 additions and 10 deletions
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4
arch/arm/dts/Makefile
View file

@ -253,10 +253,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \
zynqmp-zcu111-revA.dtb \
zynqmp-zcu1275-revA.dtb \
zynqmp-zcu1275-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1275-revA.dtb \
zynqmp-zc1275-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \

7
arch/arm/dts/zynqmp-zc1275-revA.dts → arch/arm/dts/zynqmp-zcu1275-revA.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1275
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
*
@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";
compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevA";
compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;

7
arch/arm/dts/zynqmp-zc1275-revB.dts → arch/arm/dts/zynqmp-zcu1275-revB.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZC1275 RevB
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018, Xilinx, Inc.
*
@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevB";
compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevB";
compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;

2
configs/xilinx_zynqmp_zc1275_revA_defconfig → configs/xilinx_zynqmp_zcu1275_revA_defconfig
View file

@ -30,7 +30,7 @@ CONFIG_CMD_SF=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA"
CONFIG_SPL_DM=y
CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y

2
configs/xilinx_zynqmp_zc1275_revB_defconfig → configs/xilinx_zynqmp_zcu1275_revB_defconfig
View file

@ -31,7 +31,7 @@ CONFIG_CMD_SF=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_ZYNQMP=y