mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- NPCM7xx FIU SPI driver (Jim Liu) - AT45DB641E dataflash (Luca Ellero)
This commit is contained in:
Tom Rini
commit
4209f74445
5 changed files with 468 additions and 34 deletions
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|
@ -70,6 +70,9 @@
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#define OP_WRITE_SECURITY_REVC 0x9A
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#define OP_WRITE_SECURITY 0x9B /* revision D */
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#define DATAFLASH_SHIFT_EXTID 24
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#define DATAFLASH_SHIFT_ID 40
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struct dataflash {
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uint8_t command[16];
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unsigned short page_offset; /* offset in flash address */
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@ -455,7 +458,7 @@ struct data_flash_info {
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* JEDEC id has a high byte of zero plus three data bytes:
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* the manufacturer id, then a two byte device id.
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*/
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uint32_t jedec_id;
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uint64_t jedec_id;
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/* The size listed here is what works with OP_ERASE_PAGE. */
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unsigned nr_pages;
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@ -463,6 +466,7 @@ struct data_flash_info {
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uint16_t pageoffset;
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uint16_t flags;
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#define SUP_EXTID 0x0004 /* supports extended ID data */
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#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
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#define IS_POW2PS 0x0001 /* uses 2^N byte pages */
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};
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@ -506,50 +510,31 @@ static struct data_flash_info dataflash_data[] = {
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{ "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
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{ "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
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{ "AT45DB641E", 0x1f28000100ULL, 32768, 264, 9, SUP_EXTID | SUP_POW2PS},
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{ "at45db641e", 0x1f28000100ULL, 32768, 256, 8, SUP_EXTID | SUP_POW2PS | IS_POW2PS},
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};
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static struct data_flash_info *jedec_probe(struct spi_slave *spi)
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static struct data_flash_info *jedec_lookup(struct spi_slave *spi,
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u64 jedec, bool use_extid)
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{
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int tmp;
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uint8_t id[5];
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uint32_t jedec;
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struct data_flash_info *info;
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u8 opcode = CMD_READ_ID;
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struct data_flash_info *info;
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int status;
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/*
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* JEDEC also defines an optional "extended device information"
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* string for after vendor-specific data, after the three bytes
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* we use here. Supporting some chips might require using it.
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*
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* If the vendor ID isn't Atmel's (0x1f), assume this call failed.
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* That's not an error; only rev C and newer chips handle it, and
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* only Atmel sells these chips.
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*/
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tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, sizeof(id));
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if (tmp < 0) {
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printf("dataflash: error %d reading JEDEC ID\n", tmp);
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return ERR_PTR(tmp);
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}
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if (id[0] != 0x1f)
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return NULL;
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for (info = dataflash_data;
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info < dataflash_data + ARRAY_SIZE(dataflash_data);
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info++) {
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if (use_extid && !(info->flags & SUP_EXTID))
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continue;
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jedec = id[0];
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jedec = jedec << 8;
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jedec |= id[1];
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jedec = jedec << 8;
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jedec |= id[2];
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for (tmp = 0, info = dataflash_data;
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tmp < ARRAY_SIZE(dataflash_data);
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tmp++, info++) {
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if (info->jedec_id == jedec) {
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if (info->flags & SUP_POW2PS) {
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status = dataflash_status(spi);
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if (status < 0) {
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debug("dataflash: status error %d\n",
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status);
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return NULL;
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return ERR_PTR(status);
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}
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if (status & 0x1) {
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if (info->flags & IS_POW2PS)
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@ -564,12 +549,58 @@ static struct data_flash_info *jedec_probe(struct spi_slave *spi)
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}
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}
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return ERR_PTR(-ENODEV);
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}
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static struct data_flash_info *jedec_probe(struct spi_slave *spi)
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{
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int tmp;
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uint64_t jedec;
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uint8_t id[sizeof(jedec)] = {0};
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const unsigned int id_size = 5;
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struct data_flash_info *info;
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u8 opcode = CMD_READ_ID;
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/*
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* JEDEC also defines an optional "extended device information"
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* string for after vendor-specific data, after the three bytes
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* we use here. Supporting some chips might require using it.
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*
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* If the vendor ID isn't Atmel's (0x1f), assume this call failed.
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* That's not an error; only rev C and newer chips handle it, and
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* only Atmel sells these chips.
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*/
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tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, id_size);
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if (tmp < 0) {
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printf("dataflash: error %d reading JEDEC ID\n", tmp);
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return ERR_PTR(tmp);
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}
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if (id[0] != 0x1f)
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return NULL;
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jedec = be64_to_cpup((__be64 *)id);
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/*
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* First, try to match device using extended device
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* information
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*/
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info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_EXTID, true);
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if (!IS_ERR(info))
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return info;
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/*
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* If that fails, make another pass using regular ID
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* information
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*/
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info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_ID, false);
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if (!IS_ERR(info))
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return info;
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/*
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* Treat other chips as errors ... we won't know the right page
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* size (it might be binary) even when we can tell which density
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* class is involved (legacy chip id scheme).
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*/
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printf("dataflash: JEDEC id %06x not handled\n", jedec);
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printf("dataflash: JEDEC id 0x%016llx not handled\n", jedec);
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return ERR_PTR(-ENODEV);
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}
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@ -618,6 +649,8 @@ static int spi_dataflash_probe(struct udevice *dev)
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(info->flags & SUP_POW2PS) ? 'd' : 'c');
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if (status < 0)
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goto err_status;
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else
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return status;
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}
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/*
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@ -166,6 +166,8 @@ const struct flash_info spi_nor_ids[] = {
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{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
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{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
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{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
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{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
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{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
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@ -345,6 +347,11 @@ const struct flash_info spi_nor_ids[] = {
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{
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INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{
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INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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@ -283,6 +283,12 @@ config SPI_MXIC
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can be used to access the SPI flash on platforms embedding
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this Macronix IP core.
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config NPCM_FIU_SPI
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bool "FIU driver for Nuvoton NPCM SoC"
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help
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This enables support for the Flash Interface Unit SPI controller
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in master mode.
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config NXP_FSPI
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bool "NXP FlexSPI driver"
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depends on SPI_MEM
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@ -47,6 +47,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
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obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
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obj-$(CONFIG_MXC_SPI) += mxc_spi.o
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obj-$(CONFIG_MXS_SPI) += mxs_spi.o
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obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
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obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
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obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
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obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
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387
drivers/spi/npcm_fiu_spi.c
Normal file
387
drivers/spi/npcm_fiu_spi.c
Normal file
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@ -0,0 +1,387 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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* NPCM Flash Interface Unit(FIU) SPI master controller driver.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#include <linux/iopoll.h>
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#define DW_SIZE 4
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#define CHUNK_SIZE 16
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#define XFER_TIMEOUT 1000000
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/* FIU UMA Configuration Register (UMA_CFG) */
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#define UMA_CFG_RDATSIZ_MASK GENMASK(28, 24)
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#define UMA_CFG_DBSIZ_MASK GENMASK(23, 21)
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#define UMA_CFG_WDATSIZ_MASK GENMASK(20, 16)
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#define UMA_CFG_ADDSIZ_MASK GENMASK(13, 11)
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#define UMA_CFG_RDBPCK_MASK GENMASK(9, 8)
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#define UMA_CFG_DBPCK_MASK GENMASK(7, 6)
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#define UMA_CFG_WDBPCK_MASK GENMASK(5, 4)
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#define UMA_CFG_ADBPCK_MASK GENMASK(3, 2)
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#define UMA_CFG_CMBPCK_MASK GENMASK(1, 0)
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#define UMA_CFG_CMDSIZ_SHIFT 10
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/* FIU UMA Control and Status Register (UMA_CTS) */
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#define UMA_CTS_SW_CS BIT(16)
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#define UMA_CTS_EXEC_DONE BIT(0)
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#define UMA_CTS_RDYST BIT(24)
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#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8)
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struct npcm_fiu_regs {
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unsigned int drd_cfg;
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unsigned int dwr_cfg;
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unsigned int uma_cfg;
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unsigned int uma_cts;
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unsigned int uma_cmd;
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unsigned int uma_addr;
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unsigned int prt_cfg;
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unsigned char res1[4];
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unsigned int uma_dw0;
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unsigned int uma_dw1;
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unsigned int uma_dw2;
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unsigned int uma_dw3;
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unsigned int uma_dr0;
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unsigned int uma_dr1;
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unsigned int uma_dr2;
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unsigned int uma_dr3;
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unsigned int prt_cmd0;
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unsigned int prt_cmd1;
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unsigned int prt_cmd2;
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unsigned int prt_cmd3;
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unsigned int prt_cmd4;
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unsigned int prt_cmd5;
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unsigned int prt_cmd6;
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unsigned int prt_cmd7;
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unsigned int prt_cmd8;
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unsigned int prt_cmd9;
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unsigned int stuff[4];
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unsigned int fiu_cfg;
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};
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struct npcm_fiu_priv {
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struct npcm_fiu_regs *regs;
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struct clk clk;
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};
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static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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int ret;
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|
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debug("%s: set speed %u\n", bus->name, speed);
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ret = clk_set_rate(&priv->clk, speed);
|
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if (ret < 0)
|
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return ret;
|
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|
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return 0;
|
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}
|
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|
||||
static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode)
|
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{
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return 0;
|
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}
|
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|
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static inline void activate_cs(struct npcm_fiu_regs *regs, int cs)
|
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{
|
||||
writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs), ®s->uma_cts);
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}
|
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|
||||
static inline void deactivate_cs(struct npcm_fiu_regs *regs, int cs)
|
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{
|
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writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs) | UMA_CTS_SW_CS, ®s->uma_cts);
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}
|
||||
|
||||
static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 size)
|
||||
{
|
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
|
||||
struct npcm_fiu_regs *regs = priv->regs;
|
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u32 data_reg[4];
|
||||
u32 val;
|
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int ret;
|
||||
|
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/* Set data size */
|
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writel(FIELD_PREP(UMA_CFG_RDATSIZ_MASK, size), ®s->uma_cfg);
|
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|
||||
/* Initiate the read */
|
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writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
|
||||
|
||||
/* Wait for completion */
|
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ret = readl_poll_timeout(®s->uma_cts, val,
|
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!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
|
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if (ret) {
|
||||
printf("npcm_fiu: read timeout\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Copy data from data registers */
|
||||
if (size)
|
||||
data_reg[0] = readl(®s->uma_dr0);
|
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if (size > DW_SIZE)
|
||||
data_reg[1] = readl(®s->uma_dr1);
|
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if (size > DW_SIZE * 2)
|
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data_reg[2] = readl(®s->uma_dr2);
|
||||
if (size > DW_SIZE * 3)
|
||||
data_reg[3] = readl(®s->uma_dr3);
|
||||
memcpy(buf, data_reg, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fiu_uma_write(struct udevice *bus, const u8 *buf, u32 size)
|
||||
{
|
||||
struct npcm_fiu_priv *priv = dev_get_priv(bus);
|
||||
struct npcm_fiu_regs *regs = priv->regs;
|
||||
u32 data_reg[4];
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* Set data size */
|
||||
writel(FIELD_PREP(UMA_CFG_WDATSIZ_MASK, size), ®s->uma_cfg);
|
||||
|
||||
/* Write data to data registers */
|
||||
memcpy(data_reg, buf, size);
|
||||
if (size)
|
||||
writel(data_reg[0], ®s->uma_dw0);
|
||||
if (size > DW_SIZE)
|
||||
writel(data_reg[1], ®s->uma_dw1);
|
||||
if (size > DW_SIZE * 2)
|
||||
writel(data_reg[2], ®s->uma_dw2);
|
||||
if (size > DW_SIZE * 3)
|
||||
writel(data_reg[3], ®s->uma_dw3);
|
||||
|
||||
/* Initiate the transaction */
|
||||
writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
|
||||
|
||||
/* Wait for completion */
|
||||
ret = readl_poll_timeout(®s->uma_cts, val,
|
||||
!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
|
||||
if (ret)
|
||||
printf("npcm_fiu: write timeout\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct npcm_fiu_priv *priv = dev_get_priv(bus);
|
||||
struct npcm_fiu_regs *regs = priv->regs;
|
||||
struct dm_spi_slave_plat *slave_plat =
|
||||
dev_get_parent_plat(dev);
|
||||
const u8 *tx = dout;
|
||||
u8 *rx = din;
|
||||
int bytes = bitlen / 8;
|
||||
int ret = 0;
|
||||
int len;
|
||||
|
||||
if (flags & SPI_XFER_BEGIN)
|
||||
activate_cs(regs, slave_plat->cs);
|
||||
|
||||
while (bytes) {
|
||||
len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
|
||||
if (tx) {
|
||||
ret = fiu_uma_write(bus, tx, len);
|
||||
if (ret)
|
||||
break;
|
||||
tx += len;
|
||||
} else {
|
||||
ret = fiu_uma_read(bus, rx, len);
|
||||
if (ret)
|
||||
break;
|
||||
rx += len;
|
||||
}
|
||||
bytes -= len;
|
||||
}
|
||||
|
||||
if (flags & SPI_XFER_END)
|
||||
deactivate_cs(regs, slave_plat->cs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int npcm_fiu_uma_operation(struct npcm_fiu_priv *priv, const struct spi_mem_op *op,
|
||||
u32 addr, const u8 *tx, u8 *rx, u32 nbytes, bool started)
|
||||
{
|
||||
struct npcm_fiu_regs *regs = priv->regs;
|
||||
u32 uma_cfg = 0, val;
|
||||
u32 data_reg[4];
|
||||
int ret;
|
||||
|
||||
debug("fiu_uma: opcode 0x%x, dir %d, addr 0x%x, %d bytes\n",
|
||||
op->cmd.opcode, op->data.dir, addr, nbytes);
|
||||
debug(" buswidth cmd:%d, addr:%d, dummy:%d, data:%d\n",
|
||||
op->cmd.buswidth, op->addr.buswidth, op->dummy.buswidth,
|
||||
op->data.buswidth);
|
||||
debug(" size cmd:%d, addr:%d, dummy:%d, data:%d\n",
|
||||
1, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
|
||||
debug(" tx %p, rx %p\n", tx, rx);
|
||||
|
||||
if (!started) {
|
||||
/* Send cmd/addr in the begin of an transaction */
|
||||
writel(op->cmd.opcode, ®s->uma_cmd);
|
||||
|
||||
uma_cfg |= FIELD_PREP(UMA_CFG_CMBPCK_MASK, ilog2(op->cmd.buswidth)) |
|
||||
(1 << UMA_CFG_CMDSIZ_SHIFT);
|
||||
/* Configure addr bytes */
|
||||
if (op->addr.nbytes) {
|
||||
uma_cfg |= FIELD_PREP(UMA_CFG_ADBPCK_MASK, ilog2(op->addr.buswidth)) |
|
||||
FIELD_PREP(UMA_CFG_ADDSIZ_MASK, op->addr.nbytes);
|
||||
writel(addr, ®s->uma_addr);
|
||||
}
|
||||
/* Configure dummy bytes */
|
||||
if (op->dummy.nbytes)
|
||||
uma_cfg |= FIELD_PREP(UMA_CFG_DBPCK_MASK, ilog2(op->dummy.buswidth)) |
|
||||
FIELD_PREP(UMA_CFG_DBSIZ_MASK, op->dummy.nbytes);
|
||||
}
|
||||
/* Set data bus width and data size */
|
||||
if (op->data.dir == SPI_MEM_DATA_IN && nbytes)
|
||||
uma_cfg |= FIELD_PREP(UMA_CFG_RDBPCK_MASK, ilog2(op->data.buswidth)) |
|
||||
FIELD_PREP(UMA_CFG_RDATSIZ_MASK, nbytes);
|
||||
else if (op->data.dir == SPI_MEM_DATA_OUT && nbytes)
|
||||
uma_cfg |= FIELD_PREP(UMA_CFG_WDBPCK_MASK, ilog2(op->data.buswidth)) |
|
||||
FIELD_PREP(UMA_CFG_WDATSIZ_MASK, nbytes);
|
||||
writel(uma_cfg, ®s->uma_cfg);
|
||||
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT && nbytes) {
|
||||
memcpy(data_reg, tx, nbytes);
|
||||
|
||||
if (nbytes)
|
||||
writel(data_reg[0], ®s->uma_dw0);
|
||||
if (nbytes > DW_SIZE)
|
||||
writel(data_reg[1], ®s->uma_dw1);
|
||||
if (nbytes > DW_SIZE * 2)
|
||||
writel(data_reg[2], ®s->uma_dw2);
|
||||
if (nbytes > DW_SIZE * 3)
|
||||
writel(data_reg[3], ®s->uma_dw3);
|
||||
}
|
||||
/* Initiate the transaction */
|
||||
writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
|
||||
|
||||
/* Wait for completion */
|
||||
ret = readl_poll_timeout(®s->uma_cts, val,
|
||||
!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
|
||||
if (ret) {
|
||||
printf("npcm_fiu: UMA op timeout\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (op->data.dir == SPI_MEM_DATA_IN && nbytes) {
|
||||
if (nbytes)
|
||||
data_reg[0] = readl(®s->uma_dr0);
|
||||
if (nbytes > DW_SIZE)
|
||||
data_reg[1] = readl(®s->uma_dr1);
|
||||
if (nbytes > DW_SIZE * 2)
|
||||
data_reg[2] = readl(®s->uma_dr2);
|
||||
if (nbytes > DW_SIZE * 3)
|
||||
data_reg[3] = readl(®s->uma_dr3);
|
||||
|
||||
memcpy(rx, data_reg, nbytes);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int npcm_fiu_exec_op(struct spi_slave *slave,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct udevice *bus = slave->dev->parent;
|
||||
struct npcm_fiu_priv *priv = dev_get_priv(bus);
|
||||
struct npcm_fiu_regs *regs = priv->regs;
|
||||
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
|
||||
u32 bytes, len, addr;
|
||||
const u8 *tx;
|
||||
u8 *rx;
|
||||
bool started = false;
|
||||
int ret;
|
||||
|
||||
bytes = op->data.nbytes;
|
||||
addr = (u32)op->addr.val;
|
||||
if (!bytes) {
|
||||
activate_cs(regs, slave_plat->cs);
|
||||
ret = npcm_fiu_uma_operation(priv, op, addr, NULL, NULL, 0, false);
|
||||
deactivate_cs(regs, slave_plat->cs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tx = op->data.buf.out;
|
||||
rx = op->data.buf.in;
|
||||
/*
|
||||
* Use SW-control CS for write to extend the transaction and
|
||||
* keep the Write Enable state.
|
||||
* Use HW-control CS for read to avoid clock and timing issues.
|
||||
*/
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT)
|
||||
activate_cs(regs, slave_plat->cs);
|
||||
else
|
||||
writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, slave_plat->cs) | UMA_CTS_SW_CS,
|
||||
®s->uma_cts);
|
||||
while (bytes) {
|
||||
len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
|
||||
ret = npcm_fiu_uma_operation(priv, op, addr, tx, rx, len, started);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* CS is kept low for uma write, extend the transaction */
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT)
|
||||
started = true;
|
||||
|
||||
bytes -= len;
|
||||
addr += len;
|
||||
if (tx)
|
||||
tx += len;
|
||||
if (rx)
|
||||
rx += len;
|
||||
}
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT)
|
||||
deactivate_cs(regs, slave_plat->cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int npcm_fiu_spi_probe(struct udevice *bus)
|
||||
{
|
||||
struct npcm_fiu_priv *priv = dev_get_priv(bus);
|
||||
int ret;
|
||||
|
||||
priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
|
||||
|
||||
ret = clk_get_by_index(bus, 0, &priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
|
||||
.exec_op = npcm_fiu_exec_op,
|
||||
};
|
||||
|
||||
static const struct dm_spi_ops npcm_fiu_spi_ops = {
|
||||
.xfer = npcm_fiu_spi_xfer,
|
||||
.set_speed = npcm_fiu_spi_set_speed,
|
||||
.set_mode = npcm_fiu_spi_set_mode,
|
||||
.mem_ops = &npcm_fiu_mem_ops,
|
||||
};
|
||||
|
||||
static const struct udevice_id npcm_fiu_spi_ids[] = {
|
||||
{ .compatible = "nuvoton,npcm845-fiu" },
|
||||
{ .compatible = "nuvoton,npcm750-fiu" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(npcm_fiu_spi) = {
|
||||
.name = "npcm_fiu_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = npcm_fiu_spi_ids,
|
||||
.ops = &npcm_fiu_spi_ops,
|
||||
.priv_auto = sizeof(struct npcm_fiu_priv),
|
||||
.probe = npcm_fiu_spi_probe,
|
||||
};
|
||||
Loading…
Reference in a new issue