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MX25: make use of GPIO framework for MX25 processor

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Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic 2011-08-21 10:48:19 +02:00 committed by Albert ARIBAUD
parent d8e0ca851b
commit 41eca7416c
2 changed files with 45 additions and 12 deletions
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45
arch/arm/include/asm/arch-mx25/gpio.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
/* Converts a GPIO port number and the internal bit position
* to the GPIO number
*/
#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
#endif

12
arch/arm/include/asm/arch-mx25/imx-regs.h
View file

@ -84,18 +84,6 @@ struct esdramc_regs {
u32 cdlyl; /* delay line cycle length debug */
};
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
u32 ctrl; /* control */