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ARM: tegra: misc cleanups triggered by Tegra124 review

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Use a named constant for the PLL lock bit in enable_cpu_clocks().

Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-01-24 12:46:07 -07:00 committed by Tom Warren
parent a73ca4789f
commit 41cd530d6d
2 changed files with 5 additions and 4 deletions
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6
arch/arm/cpu/arm720t/tegra114/cpu.c
View file

@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
/* Wait for PLL-X to lock */
do {
reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
} while ((reg & (1 << 27)) == 0);
} while ((reg & PLL_LOCK_MASK) == 0);
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
@ -221,9 +221,7 @@ static void power_partition(u32 status, u32 partid)
if (!is_partition_powered(status)) {
/* No, toggle the partition power state (OFF -> ON) */
debug("power_partition, toggling state\n");
clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
/* Wait for the power to come up */
while (!is_partition_powered(status))

3
arch/arm/include/asm/arch-tegra/clk_rst.h
View file

@ -160,6 +160,9 @@ struct clk_rst_ctlr {
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
#define PLL_LOCK_SHIFT 27
#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)