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ddr: imx: Add 3600 MTps rate support

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Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Marek Vasut 2023-12-02 02:48:40 +01:00 committed by Fabio Estevam
parent 88db55b054
commit 41b0f3454b
2 changed files with 5 additions and 0 deletions
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1
arch/arm/mach-imx/imx8m/clock_imx8mm.c
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@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

4
drivers/ddr/imx/phy/ddrphy_utils.c
View file

@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(933)); dram_pll_init(MHZ(933));
dram_disable_bypass(); dram_disable_bypass();
break; break;
case 3600:
dram_pll_init(MHZ(900));
dram_disable_bypass();
break;
case 3200: case 3200:
dram_pll_init(MHZ(800)); dram_pll_init(MHZ(800));
dram_disable_bypass(); dram_disable_bypass();