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Merge remote-tracking branch 'u-boot/master' into test

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This commit is contained in:
Marek Vasut 2014-05-15 00:20:54 +02:00
commit 4180b3dba2
373 changed files with 14927 additions and 10006 deletions
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2
.gitignore vendored
View file

@ -47,8 +47,8 @@
/errlog
/reloc_off
!/spl/Makefile
/spl/*
!/spl/Makefile
/tpl/
#

23
Makefile
View file

@ -6,9 +6,9 @@
#
VERSION = 2014
PATCHLEVEL = 04
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@ -285,7 +285,7 @@ export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
#
# If $(quiet) is empty, the whole command will be printed.
# If it is set to "quiet_", only the short version will be printed.
# If it is set to "quiet_", only the short version will be printed.
# If it is set to "silent_", nothing will be printed at all, since
# the variable $(silent_cmd_cc_o_c) doesn't exist.
#
@ -578,6 +578,9 @@ KBUILD_AFLAGS += -Wa,-gstabs,-S
endif
endif
# Prohibit date/time macros, which would make the build non-deterministic
KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
ifneq ($(CONFIG_SYS_TEXT_BASE),)
KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
@ -915,6 +918,16 @@ OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL
spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
ifneq ($(CONFIG_TEGRA),)
OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
@ -985,7 +998,7 @@ ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,u-boot__) common/system_map.o
endif
# The actual objects are generated when descending,
# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
@ -1424,7 +1437,7 @@ endif
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
# FIXME Should go into a make.lib or something
# FIXME Should go into a make.lib or something
# ===========================================================================
quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))

34
README
View file

@ -264,6 +264,17 @@ e.g. "make cogent_mpc8xx_config". And also configure the cogent
directory according to the instructions in cogent/README.
Sandbox Environment:
--------------------
U-Boot can be built natively to run on a Linux host using the 'sandbox'
board. This allows feature development which is not board- or architecture-
specific to be undertaken on a native platform. The sandbox is also used to
run some of U-Boot's tests.
See board/sandbox/sandbox/README.sandbox for more details.
Configuration Options:
----------------------
@ -440,6 +451,12 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_GENERIC_GLOBAL_DATA
Defines global data is initialized in generic board board_init_f().
If this macro is defined, global data is created and cleared in
generic board board_init_f(). Without this macro, architecture/board
should initialize global data before calling board_init_f().
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@ -740,6 +757,10 @@ The following options need to be configured:
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
CONFIG_SERIAL_HW_FLOW_CONTROL
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
- Console Interface:
Depending on board, define exactly one serial port
@ -3297,6 +3318,10 @@ FIT uImage format:
supports MMC, NAND and YMODEM loading of U-Boot and NAND
NAND loading of the Linux Kernel.
CONFIG_SPL_OS_BOOT
Enable booting directly to an OS from SPL.
See also: doc/README.falcon
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
@ -3372,6 +3397,10 @@ FIT uImage format:
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
CONFIG_SPL_MTD_SUPPORT
Support for the MTD subsystem within SPL. Useful for
environment on NAND support within SPL.
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
drivers/ddr/fsl/libddr.o in SPL binary.
@ -4534,6 +4563,11 @@ Low Level (hardware related) configuration options:
- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
Enables the RTC32K OSC on AM33xx based plattforms
- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Option to disable subpage write in NAND driver
driver that uses this:
drivers/mtd/nand/davinci_nand.c
Freescale QE/FMAN Firmware Support:
-----------------------------------

2
arch/arc/include/asm/config.h
View file

@ -7,6 +7,8 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#endif /*__ASM_ARC_CONFIG_H_ */

6
arch/arm/cpu/arm720t/tegra-common/spl.c
View file

@ -13,16 +13,18 @@
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h>
#include "cpu.h"
void spl_board_init(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */
writel(0xC0, &pmt->pmt_cfg_ctl);
writel(0xC0, &apb_misc->cfg_ctl);
board_init_uart_f();

4
arch/arm/cpu/arm720t/tegra114/cpu.c
View file

@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void)
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
/*
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),

4
arch/arm/cpu/arm720t/tegra124/cpu.c
View file

@ -26,8 +26,8 @@ static void enable_cpu_power_rail(void)
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
pmic_enable_cpu_vdd();

6
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
View file

@ -26,7 +26,7 @@ void davinci_enable_uart0(void)
}
#if defined(CONFIG_SYS_DA850_PLL_INIT)
void da850_waitloop(unsigned long loopcnt)
static void da850_waitloop(unsigned long loopcnt)
{
unsigned long i;
@ -34,7 +34,7 @@ void da850_waitloop(unsigned long loopcnt)
asm(" NOP");
}
int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
if (reg == davinci_pllc0_regs)
/* Unlock PLL registers. */
@ -160,7 +160,7 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
#endif /* CONFIG_SYS_DA850_PLL_INIT */
#if defined(CONFIG_SYS_DA850_DDR_INIT)
int da850_ddr_setup(void)
static int da850_ddr_setup(void)
{
unsigned long tmp;

2
arch/arm/cpu/arm926ejs/davinci/dm355.c
View file

@ -19,7 +19,7 @@ void davinci_enable_uart0(void)
}
#ifdef CONFIG_DRIVER_DAVINCI_I2C
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);

2
arch/arm/cpu/arm926ejs/davinci/dm365.c
View file

@ -12,7 +12,7 @@ void davinci_enable_uart0(void)
lpsc_on(DAVINCI_LPSC_UART0);
}
#ifdef CONFIG_DRIVER_DAVINCI_I2C
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);

2
arch/arm/cpu/arm926ejs/davinci/dm644x.c
View file

@ -47,7 +47,7 @@ void davinci_enable_emac(void)
}
#endif
#ifdef CONFIG_DRIVER_DAVINCI_I2C
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);

2
arch/arm/cpu/arm926ejs/davinci/dm646x.c
View file

@ -18,7 +18,7 @@ void davinci_enable_emac(void)
}
#endif
#ifdef CONFIG_DRIVER_DAVINCI_I2C
#ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_I2C);

1
arch/arm/cpu/armv7/Makefile
View file

@ -25,6 +25,7 @@ endif
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))

4
arch/arm/cpu/armv7/am33xx/board.c
View file

@ -142,7 +142,7 @@ int arch_misc_init(void)
return 0;
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
@ -200,9 +200,7 @@ static void watchdog_disable(void)
while (readl(&wdtimer->wdtwwps) != 0x0)
;
}
#endif
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*

2
arch/arm/cpu/armv7/am33xx/emif4.c
View file

@ -35,7 +35,7 @@ void dram_init_banksize(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;

58
arch/arm/cpu/armv7/arch_timer.c Normal file
View file

@ -0,0 +1,58 @@
/*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <div64.h>
DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
gd->arch.tbl = 0;
gd->arch.tbu = 0;
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
return 0;
}
unsigned long long get_ticks(void)
{
ulong nowl, nowu;
asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
gd->arch.tbl = nowl;
gd->arch.tbu = nowu;
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong get_timer(ulong base)
{
return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
}
void __udelay(unsigned long usec)
{
unsigned long long endtime;
endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
1000UL);
endtime += get_ticks();
while (get_ticks() < endtime)
;
}
ulong get_tbclk(void)
{
return gd->arch.timer_rate_hz;
}

17
arch/arm/cpu/armv7/keystone/Makefile Normal file
View file

@ -0,0 +1,17 @@
#
# (C) Copyright 2012-2014
# Texas Instruments Incorporated, <www.ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += aemif.o
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o

71
arch/arm/cpu/armv7/keystone/aemif.c Normal file
View file

@ -0,0 +1,71 @@
/*
* Keystone2: Asynchronous EMIF Configuration
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/emif_defs.h>
#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
#define set_config_field(reg, field, val) \
do { \
if (val != -1) { \
reg &= ~AEMIF_CFG_##field(0xffffffff); \
reg |= AEMIF_CFG_##field(val); \
} \
} while (0)
void configure_async_emif(int cs, struct async_emif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
tmp = __raw_readl(&davinci_emif_regs->nandfcr);
tmp |= (1 << cs);
__raw_writel(tmp, &davinci_emif_regs->nandfcr);
} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
tmp |= (1 << cs);
__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
}
tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
set_config_field(tmp, WR_SETUP, cfg->wr_setup);
set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
set_config_field(tmp, WR_HOLD, cfg->wr_hold);
set_config_field(tmp, RD_SETUP, cfg->rd_setup);
set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
set_config_field(tmp, RD_HOLD, cfg->rd_hold);
set_config_field(tmp, TURN_AROUND, cfg->turn_around);
set_config_field(tmp, WIDTH, cfg->width);
__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
}
void init_async_emif(int num_cs, struct async_emif_config *config)
{
int cs;
for (cs = 0; cs < num_cs; cs++)
configure_async_emif(cs, config + cs);
}

318
arch/arm/cpu/armv7/keystone/clock.c Normal file
View file

@ -0,0 +1,318 @@
/*
* Keystone2: pll initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
for (i = 0; i < 100; i++) {
sdelay(450);
if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
break;
}
}
struct pll_regs {
u32 reg0, reg1;
};
static const struct pll_regs pll_regs[] = {
[CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
[PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
[TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
[DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
[DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
};
/* Fout = Fref * NF(mult) / NR(prediv) / OD */
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(K2HK_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = K2HK_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = K2HK_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = K2HK_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = K2HK_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}
void init_pll(const struct pll_init_data *data)
{
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
pllm = data->pll_m - 1;
plld = (data->pll_d - 1) & PLL_DIV_MASK;
pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
if (data->pll == MAIN_PLL) {
/* The requered delay before main PLL configuration */
sdelay(210000);
tmp = pllctl_reg_read(data->pll, secctl);
if (tmp & (PLLCTL_BYPASS)) {
setbits_le32(pll_regs[data->pll].reg1,
BIT(MAIN_ENSAT_OFFSET));
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
PLLCTL_PLLENSRC);
sdelay(340);
pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
sdelay(21000);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
} else {
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
PLLCTL_PLLENSRC);
sdelay(340);
}
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
(pllm << 6));
/* Set the BWADJ (12 bit field) */
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
(tmp_ctl >> 8));
/*
* Set the pll divider (6 bit field) *
* PLLD[5:0] is located in MAINPLLCTL0
*/
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
(pllod << PLL_CLKOD_SHIFT));
wait_for_completion(data);
pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
pllctl_reg_setbits(data->pll, alnctl, 0x1f);
/*
* Set GOSET bit in PLLCMD to initiate the GO operation
* to change the divide
*/
pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
sdelay(1500); /* wait for the phase adj */
wait_for_completion(data);
/* Reset PLL */
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
sdelay(21000); /* Wait for a minimum of 7 us*/
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
} else if (data->pll == TETRIS_PLL) {
bwadj = pllm >> 1;
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
setbits_le32(pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
/*
* 3 Program PLLM and PLLD in PLLCTL0 register
* 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
* PLLCTL1 register. BWADJ value must be set
* to ((PLLM + 1) >> 1) – 1)
*/
tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
(pllm << 6) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
__raw_writel(tmp, pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
__raw_writel(tmp, pll_regs[data->pll].reg1);
/*
* 5 Wait for at least 5 us based on the reference
* clock (PLL reset time)
*/
sdelay(21000); /* Wait for a minimum of 7 us*/
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
/*
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
* (PLL lock time)
*/
sdelay(105000);
/* 8 disable bypass */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
} else {
setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
* process keeps state of Bypass bit while programming
* all other DDR PLL settings
*/
tmp = __raw_readl(pll_regs[data->pll].reg0);
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
/*
* Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
* bypass disabled
*/
bwadj = pllm >> 1;
tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
(pllm << PLL_MULT_SHIFT) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT);
__raw_writel(tmp, pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
/* set PLL Select (bit 13) for PASS PLL */
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
__raw_writel(tmp, pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
tmp = PLL_PLLRST;
/* Set RESET bit = 1 */
setbits_le32(pll_regs[data->pll].reg1, tmp);
/* Wait for a minimum of 7 us*/
sdelay(21000);
/* Clear RESET bit */
clrbits_le32(pll_regs[data->pll].reg1, tmp);
sdelay(105000);
/* clear BYPASS (Enable PLL Mode) */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
sdelay(21000); /* Wait for a minimum of 7 us*/
}
/*
* This is required to provide a delay between multiple
* consequent PPL configurations
*/
sdelay(210000);
}
void init_plls(int num_pll, struct pll_init_data *config)
{
int i;
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}

124
arch/arm/cpu/armv7/keystone/cmd_clock.c Normal file
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/*
* keystone2: commands for clocks
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/arch/psc_defs.h>
struct pll_init_data cmd_pll_data = {
.pll = MAIN_PLL,
.pll_m = 16,
.pll_d = 1,
.pll_od = 2,
};
int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 5)
goto pll_cmd_usage;
if (strncmp(argv[1], "pa", 2) == 0)
cmd_pll_data.pll = PASS_PLL;
else if (strncmp(argv[1], "arm", 3) == 0)
cmd_pll_data.pll = TETRIS_PLL;
else if (strncmp(argv[1], "ddr3a", 5) == 0)
cmd_pll_data.pll = DDR3A_PLL;
else if (strncmp(argv[1], "ddr3b", 5) == 0)
cmd_pll_data.pll = DDR3B_PLL;
else
goto pll_cmd_usage;
cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
cmd_pll_data.pll, cmd_pll_data.pll_m,
cmd_pll_data.pll_d, cmd_pll_data.pll_od);
init_pll(&cmd_pll_data);
return 0;
pll_cmd_usage:
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
);
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int clk;
unsigned int freq;
if (argc != 2)
goto getclk_cmd_usage;
clk = simple_strtoul(argv[1], NULL, 10);
freq = clk_get_rate(clk);
printf("clock index [%d] - frequency %u\n", clk, freq);
return 0;
getclk_cmd_usage:
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int psc_module;
int res;
if (argc != 3)
goto psc_cmd_usage;
psc_module = simple_strtoul(argv[1], NULL, 10);
if (strcmp(argv[2], "en") == 0) {
res = psc_enable_module(psc_module);
printf("psc_enable_module(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
if (strcmp(argv[2], "di") == 0) {
res = psc_disable_module(psc_module);
printf("psc_disable_module(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
if (strcmp(argv[2], "domain") == 0) {
res = psc_disable_domain(psc_module);
printf("psc_disable_domain(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
psc_cmd_usage:
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
psc, 3, 0, do_psc_cmd,
"<enable/disable psc module os disable domain>",
"<mod/domain index> <en|di|domain>\n"
"See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
);

131
arch/arm/cpu/armv7/keystone/cmd_mon.c Normal file
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/*
* K2HK: secure kernel command file
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
asm(".arch_extension sec\n\t");
static int mon_install(u32 addr, u32 dpsc, u32 freq)
{
int result;
__asm__ __volatile__ (
"stmfd r13!, {lr}\n"
"mov r0, %1\n"
"mov r1, %2\n"
"mov r2, %3\n"
"blx r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (addr), "r" (dpsc), "r" (freq)
: "cc", "r0", "r1", "r2", "memory");
return result;
}
static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
u32 addr, dpsc_base = 0x1E80000, freq;
int rcode = 0;
if (argc < 2)
return CMD_RET_USAGE;
freq = clk_get_rate(sys_clk0_6_clk);
addr = simple_strtoul(argv[1], NULL, 16);
rcode = mon_install(addr, dpsc_base, freq);
printf("## installed monitor, freq [%d], status %d\n",
freq, rcode);
return 0;
}
U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
"Install boot kernel at 'addr'",
""
);
static void core_spin(void)
{
while (1)
; /* forever */;
}
int mon_power_on(int core_id, void *ep)
{
int result;
asm volatile (
"stmfd r13!, {lr}\n"
"mov r1, %1\n"
"mov r2, %2\n"
"mov r0, #0\n"
"smc #0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id), "r" (ep)
: "cc", "r0", "r1", "r2", "memory");
return result;
}
int mon_power_off(int core_id)
{
int result;
asm volatile (
"stmfd r13!, {lr}\n"
"mov r1, %1\n"
"mov r0, #1\n"
"smc #1\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id)
: "cc", "r0", "r1", "memory");
return result;
}
int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int rcode = 0, core_id, on;
void (*fn)(void);
fn = core_spin;
if (argc < 3)
return CMD_RET_USAGE;
core_id = simple_strtoul(argv[1], NULL, 16);
on = simple_strtoul(argv[2], NULL, 16);
if (on)
rcode = mon_power_on(core_id, fn);
else
rcode = mon_power_off(core_id);
if (on) {
if (!rcode)
printf("core %d powered on successfully\n", core_id);
else
printf("core %d power on failure\n", core_id);
} else {
printf("core %d powered off successfully\n", core_id);
}
return 0;
}
U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
"Power On/Off secondary core",
"mon_power <coreid> <oper>\n"
"- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
""
);

69
arch/arm/cpu/armv7/keystone/ddr3.c Normal file
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/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/hardware.h>
#include <asm/io.h>
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
& 0x00000001) != 0x00000001)
;
__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
tmp &= ~(phy_cfg->pgcr1_mask);
tmp |= phy_cfg->pgcr1_val;
__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
__raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
__raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
__raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
__raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
tmp &= ~(phy_cfg->dcr_mask);
tmp |= phy_cfg->dcr_val;
__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
}
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}

56
arch/arm/cpu/armv7/keystone/init.c Normal file
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/*
* Keystone2: Architecture initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
void chip_configuration_unlock(void)
{
__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
}
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
#ifdef CONFIG_SOC_K2HK
share_all_segments(8);
share_all_segments(9);
share_all_segments(10); /* QM PDSP */
share_all_segments(11); /* PCIE */
#endif
return 0;
}
void reset_cpu(ulong addr)
{
volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
u32 tmp;
tmp = *rstctrl & KS2_RSTCTRL_MASK;
*rstctrl = tmp | KS2_RSTCTRL_KEY;
*rstctrl &= KS2_RSTCTRL_SWRST;
for (;;)
;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
}

376
arch/arm/cpu/armv7/keystone/keystone_nav.c Normal file
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/*
* Multicore Navigator driver for TI Keystone 2 devices.
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/keystone_nav.h>
static int soc_type =
#ifdef CONFIG_SOC_K2HK
k2hk;
#endif
struct qm_config k2hk_qm_memmap = {
.stat_cfg = 0x02a40000,
.queue = (struct qm_reg_queue *)0x02a80000,
.mngr_vbusm = 0x23a80000,
.i_lram = 0x00100000,
.proxy = (struct qm_reg_queue *)0x02ac0000,
.status_ram = 0x02a06000,
.mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
.intd_cfg = 0x02a0c000,
.desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
.region_num = 64,
.pdsp_cmd = 0x02a20000,
.pdsp_ctl = 0x02a0f000,
.pdsp_iram = 0x02a10000,
.qpool_num = 4000,
};
/*
* We are going to use only one type of descriptors - host packet
* descriptors. We staticaly allocate memory for them here
*/
struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
static struct qm_config *qm_cfg;
inline int num_of_desc_to_reg(int num_descr)
{
int j, num;
for (j = 0, num = 32; j < 15; j++, num *= 2) {
if (num_descr <= num)
return j;
}
return 15;
}
static int _qm_init(struct qm_config *cfg)
{
u32 j;
if (cfg == NULL)
return QM_ERR;
qm_cfg = cfg;
qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8;
qm_cfg->mngr_cfg->link_ram_base1 = 0;
qm_cfg->mngr_cfg->link_ram_size1 = 0;
qm_cfg->mngr_cfg->link_ram_base2 = 0;
qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
qm_cfg->desc_mem[0].start_idx = 0;
qm_cfg->desc_mem[0].desc_reg_size =
(((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
num_of_desc_to_reg(HDESC_NUM);
memset(desc_pool, 0, sizeof(desc_pool));
for (j = 0; j < HDESC_NUM; j++)
qm_push(&desc_pool[j], qm_cfg->qpool_num);
return QM_OK;
}
int qm_init(void)
{
switch (soc_type) {
case k2hk:
return _qm_init(&k2hk_qm_memmap);
}
return QM_ERR;
}
void qm_close(void)
{
u32 j;
if (qm_cfg == NULL)
return;
queue_close(qm_cfg->qpool_num);
qm_cfg->mngr_cfg->link_ram_base0 = 0;
qm_cfg->mngr_cfg->link_ram_size0 = 0;
qm_cfg->mngr_cfg->link_ram_base1 = 0;
qm_cfg->mngr_cfg->link_ram_size1 = 0;
qm_cfg->mngr_cfg->link_ram_base2 = 0;
for (j = 0; j < qm_cfg->region_num; j++) {
qm_cfg->desc_mem[j].base_addr = 0;
qm_cfg->desc_mem[j].start_idx = 0;
qm_cfg->desc_mem[j].desc_reg_size = 0;
}
qm_cfg = NULL;
}
void qm_push(struct qm_host_desc *hd, u32 qnum)
{
u32 regd;
if (!qm_cfg)
return;
cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
}
void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
void *buff_ptr, u32 buff_len)
{
hd->orig_buff_len = buff_len;
hd->buff_len = buff_len;
hd->orig_buff_ptr = (u32)buff_ptr;
hd->buff_ptr = (u32)buff_ptr;
qm_push(hd, qnum);
}
struct qm_host_desc *qm_pop(u32 qnum)
{
u32 uhd;
if (!qm_cfg)
return NULL;
uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
if (uhd)
cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
return (struct qm_host_desc *)uhd;
}
struct qm_host_desc *qm_pop_from_free_pool(void)
{
if (!qm_cfg)
return NULL;
return qm_pop(qm_cfg->qpool_num);
}
void queue_close(u32 qnum)
{
struct qm_host_desc *hd;
while ((hd = qm_pop(qnum)))
;
}
/*
* DMA API
*/
struct pktdma_cfg k2hk_netcp_pktdma = {
.global = (struct global_ctl_regs *)0x02004000,
.tx_ch = (struct tx_chan_regs *)0x02004400,
.tx_ch_num = 9,
.rx_ch = (struct rx_chan_regs *)0x02004800,
.rx_ch_num = 26,
.tx_sched = (u32 *)0x02004c00,
.rx_flows = (struct rx_flow_regs *)0x02005000,
.rx_flow_num = 32,
.rx_free_q = 4001,
.rx_rcv_q = 4002,
.tx_snd_q = 648,
};
struct pktdma_cfg *netcp;
static int netcp_rx_disable(void)
{
u32 j, v, k;
for (j = 0; j < netcp->rx_ch_num; j++) {
v = readl(&netcp->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
v = readl(&netcp->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
}
/* Clear all of the flow registers */
for (j = 0; j < netcp->rx_flow_num; j++) {
writel(0, &netcp->rx_flows[j].control);
writel(0, &netcp->rx_flows[j].tags);
writel(0, &netcp->rx_flows[j].tag_sel);
writel(0, &netcp->rx_flows[j].fdq_sel[0]);
writel(0, &netcp->rx_flows[j].fdq_sel[1]);
writel(0, &netcp->rx_flows[j].thresh[0]);
writel(0, &netcp->rx_flows[j].thresh[1]);
writel(0, &netcp->rx_flows[j].thresh[2]);
}
return QM_OK;
}
static int netcp_tx_disable(void)
{
u32 j, v, k;
for (j = 0; j < netcp->tx_ch_num; j++) {
v = readl(&netcp->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
v = readl(&netcp->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
}
return QM_OK;
}
static int _netcp_init(struct pktdma_cfg *netcp_cfg,
struct rx_buff_desc *rx_buffers)
{
u32 j, v;
struct qm_host_desc *hd;
u8 *rx_ptr;
if (netcp_cfg == NULL || rx_buffers == NULL ||
rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
return QM_ERR;
netcp = netcp_cfg;
netcp->rx_flow = rx_buffers->rx_flow;
/* init rx queue */
rx_ptr = rx_buffers->buff_ptr;
for (j = 0; j < rx_buffers->num_buffs; j++) {
hd = qm_pop(qm_cfg->qpool_num);
if (hd == NULL)
return QM_ERR;
qm_buff_push(hd, netcp->rx_free_q,
rx_ptr, rx_buffers->buff_len);
rx_ptr += rx_buffers->buff_len;
}
netcp_rx_disable();
/* configure rx channels */
v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
writel(v, &netcp->rx_flows[netcp->rx_flow].control);
writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
netcp->rx_free_q);
writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
for (j = 0; j < netcp->rx_ch_num; j++)
writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
/* configure tx channels */
/* Disable loopback in the tx direction */
writel(0, &netcp->global->emulation_control);
/* TODO: make it dependend on a soc type variable */
#ifdef CONFIG_SOC_K2HK
/* Set QM base address, only for K2x devices */
writel(0x23a80000, &netcp->global->qm_base_addr[0]);
#endif
/* Enable all channels. The current state isn't important */
for (j = 0; j < netcp->tx_ch_num; j++) {
writel(0, &netcp->tx_ch[j].cfg_b);
writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
}
return QM_OK;
}
int netcp_init(struct rx_buff_desc *rx_buffers)
{
switch (soc_type) {
case k2hk:
_netcp_init(&k2hk_netcp_pktdma, rx_buffers);
return QM_OK;
}
return QM_ERR;
}
int netcp_close(void)
{
if (!netcp)
return QM_ERR;
netcp_tx_disable();
netcp_rx_disable();
queue_close(netcp->rx_free_q);
queue_close(netcp->rx_rcv_q);
queue_close(netcp->tx_snd_q);
return QM_OK;
}
int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
{
struct qm_host_desc *hd;
hd = qm_pop(qm_cfg->qpool_num);
if (hd == NULL)
return QM_ERR;
hd->desc_info = num_bytes;
hd->swinfo[2] = swinfo2;
hd->packet_info = qm_cfg->qpool_num;
qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
return QM_OK;
}
void *netcp_recv(u32 **pkt, int *num_bytes)
{
struct qm_host_desc *hd;
hd = qm_pop(netcp->rx_rcv_q);
if (!hd)
return NULL;
*pkt = (u32 *)hd->buff_ptr;
*num_bytes = hd->desc_info & 0x3fffff;
return hd;
}
void netcp_release_rxhd(void *hd)
{
struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
_hd->buff_len = _hd->orig_buff_len;
_hd->buff_ptr = _hd->orig_buff_ptr;
qm_push(_hd, netcp->rx_free_q);
}

68
arch/arm/cpu/armv7/keystone/msmc.c Normal file
View file

@ -0,0 +1,68 @@
/*
* MSMC controller utilities
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
struct mpax {
u32 mpaxl;
u32 mpaxh;
};
struct msms_regs {
u32 pid;
u32 _res_04;
u32 smcerrar;
u32 smcerrxr;
u32 smedcc;
u32 smcea;
u32 smsecc;
u32 smpfar;
u32 smpfxr;
u32 smpfr;
u32 smpfcr;
u32 _res_2c;
u32 sbndc[8];
u32 sbndm;
u32 sbnde;
u32 _res_58;
u32 cfglck;
u32 cfgulck;
u32 cfglckstat;
u32 sms_mpax_lck;
u32 sms_mpax_ulck;
u32 sms_mpax_lckstat;
u32 ses_mpax_lck;
u32 ses_mpax_ulck;
u32 ses_mpax_lckstat;
u32 smestat;
u32 smirstat;
u32 smirc;
u32 smiestat;
u32 smiec;
u32 _res_94_c0[12];
u32 smncerrar;
u32 smncerrxr;
u32 smncea;
u32 _res_d0_1fc[76];
struct mpax sms[16][8];
struct mpax ses[16][8];
};
void share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {
msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
}
}

237
arch/arm/cpu/armv7/keystone/psc.c Normal file
View file

@ -0,0 +1,237 @@
/*
* Keystone: PSC configuration module
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/psc_defs.h>
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
#ifdef CONFIG_SOC_K2HK
#define DEVICE_PSC_BASE K2HK_PSC_BASE
#endif
int psc_delay(void)
{
udelay(10);
return 10;
}
/*
* FUNCTION PURPOSE: Wait for end of transitional state
*
* DESCRIPTION: Polls pstat for the selected domain and waits for transitions
* to be complete.
*
* Since this is boot loader code it is *ASSUMED* that interrupts
* are disabled and no other core is mucking around with the psc
* at the same time.
*
* Returns 0 when the domain is free. Returns -1 if a timeout
* occurred waiting for the completion.
*/
int psc_wait(u32 domain_num)
{
u32 retry;
u32 ptstat;
/*
* Do nothing if the power domain is in transition. This should never
* happen since the boot code is the only software accesses psc.
* It's still remotely possible that the hardware state machines
* initiate transitions.
* Don't trap if the domain (or a module in this domain) is
* stuck in transition.
*/
retry = 0;
do {
ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
return -1;
return 0;
}
u32 psc_get_domain_num(u32 mod_num)
{
u32 domain_num;
/* Get the power domain associated with the module number */
domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
return domain_num;
}
/*
* FUNCTION PURPOSE: Power up/down a module
*
* DESCRIPTION: Powers up/down the requested module and the associated power
* domain if required. No action is taken it the module is
* already powered up/down.
*
* This only controls modules. The domain in which the module
* resides will be left in the power on state. Multiple modules
* can exist in a power domain, so powering down the domain based
* on a single module is not done.
*
* Returns 0 on success, -1 if the module can't be powered up, or
* if there is a timeout waiting for the transition.
*/
int psc_set_state(u32 mod_num, u32 state)
{
u32 domain_num;
u32 pdctl;
u32 mdctl;
u32 ptcmd;
u32 reset_iso;
u32 v;
/*
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
/* Wait for the status of the domain/module to be non-transitional */
if (psc_wait(domain_num) != 0)
return -1;
/*
* Perform configuration even if the current status matches the
* existing state
*
* Set the next state of the power domain to on. It's OK if the domain
* is always on. This code will not ever power down a domain, so no
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
}
/*
* FUNCTION PURPOSE: Power up a module
*
* DESCRIPTION: Powers up the requested module and the associated power domain
* if required. No action is taken it the module is already
* powered up.
*
* Returns 0 on success, -1 if the module can't be powered up, or
* if there is a timeout waiting for the transition.
*/
int psc_enable_module(u32 mod_num)
{
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
}
/*
* FUNCTION PURPOSE: Power down a module
*
* DESCRIPTION: Powers down the requested module.
*
* Returns 0 on success, -1 on failure or timeout.
*/
int psc_disable_module(u32 mod_num)
{
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
/*
* FUNCTION PURPOSE: Set the reset isolation bit in mdctl
*
* DESCRIPTION: The reset isolation enable bit is set. The state of the module
* is not changed. Returns 0 if the module config showed that
* reset isolation is supported. Returns 1 otherwise. This is not
* an error, but setting the bit in mdctl has no effect.
*/
int psc_set_reset_iso(u32 mod_num)
{
u32 v;
u32 mdctl;
/* Set the reset isolation bit */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
return 1;
}
/*
* FUNCTION PURPOSE: Disable a power domain
*
* DESCRIPTION: The power domain is disabled
*/
int psc_disable_domain(u32 domain_num)
{
u32 pdctl;
u32 ptcmd;
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}

45
arch/arm/cpu/armv7/keystone/spl.c Normal file
View file

@ -0,0 +1,45 @@
/*
* common spl init code
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <config.h>
#include <ns16550.h>
#include <malloc.h>
#include <spl.h>
#include <spi_flash.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
}
void spl_board_init(void)
{
spl_init_keystone_plls();
preloader_console_init();
}
u32 spl_boot_device(void)
{
#if defined(CONFIG_SPL_SPI_LOAD)
return BOOT_DEVICE_SPI;
#else
puts("Unknown boot device\n");
hang();
#endif
}

11
arch/arm/cpu/armv7/omap-common/boot-common.c
View file

@ -56,6 +56,17 @@ void save_omap_boot_params(void)
*((u32 *)(dev_data + BOOT_MODE_OFFSET));
}
}
#ifdef CONFIG_DRA7XX
/*
* We get different values for QSPI_1 and QSPI_4 being used, but
* don't actually care about this difference. Rather than
* mangle the later code, if we're coming in as QSPI_4 just
* change to the QSPI_1 value.
*/
if (gd->arch.omap_boot_params.omap_bootdevice == 11)
gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI;
#endif
}
#ifdef CONFIG_SPL_BUILD

21
arch/arm/cpu/armv7/omap-common/utils.c
View file

@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
while (1) {
@ -39,3 +40,23 @@ void cancel_out(u32 *num, u32 *den, u32 den_limit)
*den = (*den + 1) / 2;
}
}
void __weak usb_fake_mac_from_die_id(u32 *id)
{
uint8_t device_mac[6];
if (!getenv("usbethaddr")) {
/*
* create a fake MAC address from the processor ID code.
* first byte is 0x02 to signify locally administered.
*/
device_mac[0] = 0x02;
device_mac[1] = id[3] & 0xff;
device_mac[2] = id[2] & 0xff;
device_mac[3] = id[1] & 0xff;
device_mac[4] = id[0] & 0xff;
device_mac[5] = (id[0] >> 8) & 0xff;
eth_setenv_enetaddr("usbethaddr", device_mac);
}
}

4
arch/arm/cpu/armv7/omap3/board.c
View file

@ -290,8 +290,8 @@ void watchdog_init(void)
* should not be running and does not generate a PRCM reset.
*/
sr32(&prcm_base->fclken_wkup, 5, 1, 1);
sr32(&prcm_base->iclken_wkup, 5, 1, 1);
setbits_le32(&prcm_base->fclken_wkup, 0x20);
setbits_le32(&prcm_base->iclken_wkup, 0x20);
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
writel(WD_UNLOCK1, &wd2_base->wspr);

353
arch/arm/cpu/armv7/omap3/clock.c
View file

@ -132,9 +132,9 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
if (xip_safe) {
/*
* CORE DPLL
* sr32(CM_CLKSEL2_EMU) set override to work when asleep
*/
sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
@ -144,37 +144,50 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, (CORE_M3X2 + 1) << 16) ;
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel1_pll,
0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll,
0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll,
0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&prcm_base->clksel1_pll, 6, 1, 0);
clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x0000000C, CORE_L4_DIV << 2);
/* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000003, CORE_L3_DIV);
/* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
clrsetbits_le32(&prcm_base->clksel_gfx,
0x00000007, GFX_DIV);
/* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
clrsetbits_le32(&prcm_base->clksel_wkup,
0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
clrsetbits_le32(&prcm_base->clken_pll,
0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
@ -186,29 +199,29 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&p0, 4, 4, ptr->fsel);
clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&p1, 27, 5, ptr->m2);
clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&p1, 16, 11, ptr->m);
clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&p1, 8, 7, ptr->n);
clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&p1, 6, 1, 0);
clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
sr32(&p2, 8, 4, CORE_SSI_DIV);
clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
sr32(&p2, 4, 2, CORE_FUSB_DIV);
clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
sr32(&p2, 2, 2, CORE_L4_DIV);
clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
sr32(&p2, 0, 2, CORE_L3_DIV);
clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
@ -225,7 +238,7 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/*
@ -234,33 +247,38 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
* and then the actual divisor value
*/
/* M6 */
sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
clrsetbits_le32(&prcm_base->clksel1_emu,
0x1F000000, (PER_M6X2 + 1) << 24);
clrsetbits_le32(&prcm_base->clksel1_emu,
0x1F000000, PER_M6X2 << 24);
/* M5 */
sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
/* M4 */
sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
/* M3 */
sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
clrsetbits_le32(&prcm_base->clksel_dss,
0x00001F00, (PER_M3X2 + 1) << 8);
clrsetbits_le32(&prcm_base->clksel_dss,
0x00001F00, PER_M3X2 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* Workaround end */
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel2_pll,
0x0007FF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
@ -273,13 +291,18 @@ static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
/* set M2 (usbtll_fck) */
clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
/* set m (11-bit multiplier) */
clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
/* set n (7-bit divider)*/
clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
/* FREQSEL */
clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
/* lock mode */
clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
@ -294,16 +317,20 @@ static void mpu_init_34xx(u32 sil_index, u32 clk_index)
/* MPU DPLL (unlocked already) */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
0x0000007F, ptr->n);
/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x000000F0, ptr->fsel << 4);
}
static void iva_init_34xx(u32 sil_index, u32 clk_index)
@ -316,23 +343,29 @@ static void iva_init_34xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken_pll_iva2,
0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
0x0000007F, ptr->n);
/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
clrsetbits_le32(&prcm_base->clken_pll_iva2,
0x000000F0, ptr->fsel << 4);
/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll_iva2,
0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
@ -357,41 +390,54 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
/* CORE DPLL */
/* Select relock bypass: CM_CLKEN_PLL[0:2] */
sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel1_pll,
0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll,
0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll,
0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&prcm_base->clksel1_pll, 6, 1, 0);
clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x0000000C, CORE_L4_DIV << 2);
/* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
clrsetbits_le32(&prcm_base->clksel_core,
0x00000003, CORE_L3_DIV);
/* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
clrsetbits_le32(&prcm_base->clksel_gfx,
0x00000007, GFX_DIV_36X);
/* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
clrsetbits_le32(&prcm_base->clksel_wkup,
0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
clrsetbits_le32(&prcm_base->clken_pll,
0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
@ -403,29 +449,29 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&p0, 4, 4, ptr->fsel);
clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&p1, 27, 5, ptr->m2);
clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&p1, 16, 11, ptr->m);
clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&p1, 8, 7, ptr->n);
clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&p1, 6, 1, 0);
clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
sr32(&p2, 8, 4, CORE_SSI_DIV);
clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
sr32(&p2, 4, 2, CORE_FUSB_DIV);
clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
sr32(&p2, 2, 2, CORE_L4_DIV);
clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
sr32(&p2, 0, 2, CORE_L3_DIV);
clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
@ -444,35 +490,35 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
ptr += clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
@ -485,12 +531,16 @@ static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
/* set M2 (usbtll_fck) */
clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
/* set m (11-bit multiplier) */
clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
/* set n (7-bit divider)*/
clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
/* lock mode */
clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
@ -505,13 +555,13 @@ static void mpu_init_36xx(u32 sil_index, u32 clk_index)
/* MPU DPLL (unlocked already */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
}
static void iva_init_36xx(u32 sil_index, u32 clk_index)
@ -524,20 +574,20 @@ static void iva_init_36xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
@ -561,16 +611,16 @@ void prcm_init(void)
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
clk_index = sys_clkin_sel;
}
@ -587,12 +637,14 @@ void prcm_init(void)
* input divider to /1 as it should never set to /6.5
* in this case.
*/
if (sys_clkin_sel != 1) /* 13 MHz */
if (sys_clkin_sel != 1) { /* 13 MHz */
/* Bit 8: DPLL4_CLKINP_DIV */
sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
}
/* Unlock MPU DPLL (slows things down, and needed later) */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
@ -603,7 +655,8 @@ void prcm_init(void)
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
@ -620,7 +673,8 @@ void prcm_init(void)
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
@ -633,14 +687,15 @@ void prcm_init(void)
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
clrsetbits_le32(&prcm_base->clken_pll_mpu,
0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
sr32(&prcm_base->clksel_per, 0, 8, 0xff);
sr32(&prcm_base->clksel_wkup, 0, 1, 1);
setbits_le32(&prcm_base->clksel_per, 0x000000FF);
setbits_le32(&prcm_base->clksel_wkup, 1);
sdelay(5000);
}
@ -653,16 +708,16 @@ void ehci_clocks_enable(void)
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
setbits_le32(&prcm_base->iclken_usbhost, 1);
/*
* Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
* and USBHOST_120M_FCLK (USBHOST_FCLK2)
*/
sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
/* Enable USBTTL_ICLK */
sr32(&prcm_base->iclken3_core, 2, 1, 1);
setbits_le32(&prcm_base->iclken3_core, 0x00000004);
/* Enable USBTTL_FCLK */
sr32(&prcm_base->fclken3_core, 2, 1, 1);
setbits_le32(&prcm_base->fclken3_core, 0x00000004);
}
/******************************************************************************
@ -673,62 +728,62 @@ void per_clocks_enable(void)
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
setbits_le32(&prcm_base->fclken1_core, 0x00002000);
setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* UART 3 Clocks */
sr32(&prcm_base->fclken_per, 11, 1, 0x1);
sr32(&prcm_base->iclken_per, 11, 1, 0x1);
setbits_le32(&prcm_base->fclken_per, 0x00000800);
setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
#ifdef CONFIG_OMAP3_GPIO_2
sr32(&prcm_base->fclken_per, 13, 1, 1);
sr32(&prcm_base->iclken_per, 13, 1, 1);
setbits_le32(&prcm_base->fclken_per, 0x00002000);
setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
#ifdef CONFIG_OMAP3_GPIO_3
sr32(&prcm_base->fclken_per, 14, 1, 1);
sr32(&prcm_base->iclken_per, 14, 1, 1);
setbits_le32(&prcm_base->fclken_per, 0x00004000);
setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
#ifdef CONFIG_OMAP3_GPIO_4
sr32(&prcm_base->fclken_per, 15, 1, 1);
sr32(&prcm_base->iclken_per, 15, 1, 1);
setbits_le32(&prcm_base->fclken_per, 0x00008000);
setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
#ifdef CONFIG_OMAP3_GPIO_5
sr32(&prcm_base->fclken_per, 16, 1, 1);
sr32(&prcm_base->iclken_per, 16, 1, 1);
setbits_le32(&prcm_base->fclken_per, 0x00010000);
setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
#ifdef CONFIG_OMAP3_GPIO_6
sr32(&prcm_base->fclken_per, 17, 1, 1);
sr32(&prcm_base->iclken_per, 17, 1, 1);
setbits_le32(&prcm_base->fclken_per, 0x00020000);
setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif
#ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
setbits_le32(&prcm_base->fclken1_core, 0x00038000);
setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
#endif
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
if (get_cpu_family() != CPU_AM35XX)
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
if (get_cpu_family() != CPU_AM35XX) {
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
}
sdelay(1000);

19
arch/arm/cpu/armv7/omap3/sys_info.c
View file

@ -40,12 +40,24 @@ static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
"1.2"};
#endif /* CONFIG_DISPLAY_CPUINFO */
/*****************************************************************
* get_dieid(u32 *id) - read die ID
*****************************************************************/
void get_dieid(u32 *id)
{
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
id[3] = readl(&id_base->die_id_0);
id[2] = readl(&id_base->die_id_1);
id[1] = readl(&id_base->die_id_2);
id[0] = readl(&id_base->die_id_3);
}
/*****************************************************************
* dieid_num_r(void) - read and set die ID
*****************************************************************/
void dieid_num_r(void)
{
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
char *uid_s, die_id[34];
u32 id[4];
@ -54,10 +66,7 @@ void dieid_num_r(void)
uid_s = getenv("dieid#");
if (uid_s == NULL) {
id[3] = readl(&id_base->die_id_0);
id[2] = readl(&id_base->die_id_1);
id[1] = readl(&id_base->die_id_2);
id[0] = readl(&id_base->die_id_3);
get_dieid(id);
sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
setenv("dieid#", die_id);
uid_s = die_id;

13
arch/arm/cpu/armv7/syslib.c
View file

@ -24,19 +24,6 @@ void sdelay(unsigned long loops)
"bne 1b":"=r" (loops):"0"(loops));
}
/*****************************************************************
* sr32 - clear & set a value in a bit range for a 32 bit address
*****************************************************************/
void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
{
u32 tmp, msk = 0;
msk = 1 << num_bits;
--msk;
tmp = readl((u32)addr) & ~(msk << start_bit);
tmp |= value << start_bit;
writel(tmp, (u32)addr);
}
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.

6
arch/arm/cpu/tegra-common/Makefile
View file

@ -7,6 +7,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ap.o
obj-y += board.o
obj-y += cache.o
obj-y += clock.o
obj-y += lowlevel_init.o
obj-y += ap.o board.o clock.o cache.o
obj-y += pinmux-common.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o

508
arch/arm/cpu/tegra-common/pinmux-common.c Normal file
View file

@ -0,0 +1,508 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
/* return 1 if a pingrp is in range */
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) \
(((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
/* return 1 if a pin_pupd_is in range */
#define pmux_pin_pupd_isvalid(pupd) \
(((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
/* return 1 if a pin_tristate_is in range */
#define pmux_pin_tristate_isvalid(tristate) \
(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) \
(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) \
(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) \
(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
#ifdef TEGRA_PMX_HAS_RCV_SEL
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
#if defined(CONFIG_TEGRA20)
#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
#define TRI_SHIFT(grp) ((grp) % 32)
#else
#define REG(pin) _R(0x3000 + ((pin) * 4))
#define MUX_REG(pin) REG(pin)
#define MUX_SHIFT(pin) 0
#define PULL_REG(pin) REG(pin)
#define PULL_SHIFT(pin) 2
#define TRI_REG(pin) REG(pin)
#define TRI_SHIFT(pin) 4
#endif /* CONFIG_TEGRA20 */
#define DRV_REG(group) _R(0x868 + ((group) * 4))
#define IO_SHIFT 5
#define OD_SHIFT 6
#define LOCK_SHIFT 7
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
u32 *reg = MUX_REG(pin);
int i, mux = -1;
u32 val;
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
if (func >= PMUX_FUNC_RSVD1) {
mux = (func - PMUX_FUNC_RSVD1) & 3;
} else {
/* Search for the appropriate function */
for (i = 0; i < 4; i++) {
if (tegra_soc_pingroups[pin].funcs[i] == func) {
mux = i;
break;
}
}
}
assert(mux != -1);
val = readl(reg);
val &= ~(3 << MUX_SHIFT(pin));
val |= (mux << MUX_SHIFT(pin));
writel(val, reg);
}
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
{
u32 *reg = PULL_REG(pin);
u32 val;
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
val = readl(reg);
val &= ~(3 << PULL_SHIFT(pin));
val |= (pupd << PULL_SHIFT(pin));
writel(val, reg);
}
static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
{
u32 *reg = TRI_REG(pin);
u32 val;
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_tristate_isvalid(tri));
val = readl(reg);
if (tri == PMUX_TRI_TRISTATE)
val |= (1 << TRI_SHIFT(pin));
else
val &= ~(1 << TRI_SHIFT(pin));
writel(val, reg);
}
void pinmux_tristate_enable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
}
void pinmux_tristate_disable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
}
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
u32 *reg = REG(pin);
u32 val;
if (io == PMUX_PIN_NONE)
return;
/* Error check on pin and io */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
val = readl(reg);
if (io == PMUX_PIN_INPUT)
val |= (io & 1) << IO_SHIFT;
else
val &= ~(1 << IO_SHIFT);
writel(val, reg);
}
static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
u32 *reg = REG(pin);
u32 val;
if (lock == PMUX_PIN_LOCK_DEFAULT)
return;
/* Error check on pin and lock */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
val = readl(reg);
if (lock == PMUX_PIN_LOCK_ENABLE) {
val |= (1 << LOCK_SHIFT);
} else {
if (val & (1 << LOCK_SHIFT))
printf("%s: Cannot clear LOCK bit!\n", __func__);
val &= ~(1 << LOCK_SHIFT);
}
writel(val, reg);
return;
}
static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
u32 *reg = REG(pin);
u32 val;
if (od == PMUX_PIN_OD_DEFAULT)
return;
/* Error check on pin and od */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_od_isvalid(od));
val = readl(reg);
if (od == PMUX_PIN_OD_ENABLE)
val |= (1 << OD_SHIFT);
else
val &= ~(1 << OD_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
u32 *reg = REG(pin);
u32 val;
if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
return;
/* Error check on pin and ioreset */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_ioreset_isvalid(ioreset));
val = readl(reg);
if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
val |= (1 << IO_RESET_SHIFT);
else
val &= ~(1 << IO_RESET_SHIFT);
writel(val, reg);
return;
}
#ifdef TEGRA_PMX_HAS_RCV_SEL
static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
enum pmux_pin_rcv_sel rcv_sel)
{
u32 *reg = REG(pin);
u32 val;
if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
return;
/* Error check on pin and rcv_sel */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
val = readl(reg);
if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
val |= (1 << RCV_SEL_SHIFT);
else
val &= ~(1 << RCV_SEL_SHIFT);
writel(val, reg);
return;
}
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
enum pmux_pingrp pin = config->pingrp;
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
pinmux_set_tristate(pin, config->tristate);
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
pinmux_set_io(pin, config->io);
pinmux_set_lock(pin, config->lock);
pinmux_set_od(pin, config->od);
pinmux_set_ioreset(pin, config->ioreset);
#ifdef TEGRA_PMX_HAS_RCV_SEL
pinmux_set_rcv_sel(pin, config->rcv_sel);
#endif
#endif
}
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len)
{
int i;
for (i = 0; i < len; i++)
pinmux_config_pingrp(&config[i]);
}
#ifdef TEGRA_PMX_HAS_DRVGRPS
#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
#define pmux_slw_isvalid(slw) \
(((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
#define pmux_drv_isvalid(drv) \
(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#define HSM_SHIFT 2
#define SCHMT_SHIFT 3
#define LPMD_SHIFT 4
#define LPMD_MASK (3 << LPMD_SHIFT)
#define DRVDN_SHIFT 12
#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
#define DRVUP_SHIFT 20
#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
#define SLWR_SHIFT 28
#define SLWR_MASK (3 << SLWR_SHIFT)
#define SLWF_SHIFT 30
#define SLWF_MASK (3 << SLWF_SHIFT)
static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwf == PMUX_SLWF_NONE)
return;
/* Error check on pad and slwf */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwf));
val = readl(reg);
val &= ~SLWF_MASK;
val |= (slwf << SLWF_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwr == PMUX_SLWR_NONE)
return;
/* Error check on pad and slwr */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwr));
val = readl(reg);
val &= ~SLWR_MASK;
val |= (slwr << SLWR_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvup == PMUX_DRVUP_NONE)
return;
/* Error check on pad and drvup */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvup));
val = readl(reg);
val &= ~DRVUP_MASK;
val |= (drvup << DRVUP_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PMUX_DRVDN_NONE)
return;
/* Error check on pad and drvdn */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvdn));
val = readl(reg);
val &= ~DRVDN_MASK;
val |= (drvdn << DRVDN_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PMUX_LPMD_NONE)
return;
/* Error check pad and lpmd value */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_lpmd_isvalid(lpmd));
val = readl(reg);
val &= ~LPMD_MASK;
val |= (lpmd << LPMD_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (schmt == PMUX_SCHMT_NONE)
return;
/* Error check pad */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_schmt_isvalid(schmt));
val = readl(reg);
if (schmt == PMUX_SCHMT_ENABLE)
val |= (1 << SCHMT_SHIFT);
else
val &= ~(1 << SCHMT_SHIFT);
writel(val, reg);
return;
}
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (hsm == PMUX_HSM_NONE)
return;
/* Error check pad */
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_hsm_isvalid(hsm));
val = readl(reg);
if (hsm == PMUX_HSM_ENABLE)
val |= (1 << HSM_SHIFT);
else
val &= ~(1 << HSM_SHIFT);
writel(val, reg);
return;
}
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
{
enum pmux_drvgrp grp = config->drvgrp;
pinmux_set_drvup_slwf(grp, config->slwf);
pinmux_set_drvdn_slwr(grp, config->slwr);
pinmux_set_drvup(grp, config->drvup);
pinmux_set_drvdn(grp, config->drvdn);
pinmux_set_lpmd(grp, config->lpmd);
pinmux_set_schmt(grp, config->schmt);
pinmux_set_hsm(grp, config->hsm);
}
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len)
{
int i;
for (i = 0; i < len; i++)
pinmux_config_drvgrp(&config[i]);
}
#endif /* TEGRA_PMX_HAS_DRVGRPS */

28
arch/arm/cpu/tegra114-common/funcmux.c
View file

@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GMI:
pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
PMUX_FUNC_UARTD);
pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
pinmux_tristate_disable(PINGRP_GMI_A16);
pinmux_tristate_disable(PINGRP_GMI_A17);
pinmux_tristate_disable(PINGRP_GMI_A18);
pinmux_tristate_disable(PINGRP_GMI_A19);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
break;
}
break;

1015
arch/arm/cpu/tegra114-common/pinmux.c
View file

File diff suppressed because it is too large Load diff

38
arch/arm/cpu/tegra124-common/funcmux.c
View file

@ -20,20 +20,20 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
pinmux_tristate_disable(PINGRP_GPIO_PJ7);
pinmux_tristate_disable(PINGRP_GPIO_PB0);
pinmux_tristate_disable(PINGRP_GPIO_PB1);
pinmux_tristate_disable(PINGRP_GPIO_PK7);
pinmux_tristate_disable(PMUX_PINGRP_PJ7);
pinmux_tristate_disable(PMUX_PINGRP_PB0);
pinmux_tristate_disable(PMUX_PINGRP_PB1);
pinmux_tristate_disable(PMUX_PINGRP_PK7);
break;
}
break;
@ -41,14 +41,16 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_KBC:
pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
PMUX_FUNC_UARTA);
pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
pinmux_tristate_disable(PINGRP_KB_ROW9);
pinmux_tristate_disable(PINGRP_KB_ROW10);
pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
break;
}
break;

1018
arch/arm/cpu/tegra124-common/pinmux.c
View file

File diff suppressed because it is too large Load diff

2
arch/arm/cpu/tegra20-common/emc.c
View file

@ -8,7 +8,7 @@
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch/apb_misc.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/tegra.h>

181
arch/arm/cpu/tegra20-common/funcmux.c
View file

@ -14,9 +14,9 @@
* The PINMUX macro is used to set up pinmux tables.
*/
#define PINMUX(grp, mux, pupd, tri) \
{PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
{PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
static const struct pingroup_config disp1_default[] = {
static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
PINMUX(LHP0, DISPA, NORMAL, NORMAL),
PINMUX(LHP1, DISPA, NORMAL, NORMAL),
@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_IRRX);
pinmux_tristate_disable(PMUX_PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_UAA);
pinmux_tristate_disable(PINGRP_UAB);
pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_UAA);
pinmux_tristate_disable(PMUX_PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_GPU);
pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_SDIO1);
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
}
@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config)
* state the group to avoid driving any signal onto it
* until we know what's connected.
*/
pinmux_tristate_enable(PINGRP_SDB);
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_tristate_enable(PMUX_PINGRP_SDB);
pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
}
break;
case PERIPH_ID_UART2:
if (config == FUNCMUX_UART2_UAD) {
pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
pinmux_tristate_disable(PINGRP_UAD);
pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
pinmux_tristate_disable(PMUX_PINGRP_UAD);
}
break;
case PERIPH_ID_UART4:
if (config == FUNCMUX_UART4_GMC) {
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PINGRP_GMC);
pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PMUX_PINGRP_GMC);
}
break;
case PERIPH_ID_DVC_I2C:
/* there is only one selection, pinmux_config is ignored */
if (config == FUNCMUX_DVC_I2CP) {
pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
pinmux_tristate_disable(PINGRP_I2CP);
pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
pinmux_tristate_disable(PMUX_PINGRP_I2CP);
}
break;
case PERIPH_ID_I2C1:
/* support pinmux_config of 0 for now, */
if (config == FUNCMUX_I2C1_RM) {
pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
pinmux_tristate_disable(PINGRP_RM);
pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
pinmux_tristate_disable(PMUX_PINGRP_RM);
}
break;
case PERIPH_ID_I2C2: /* I2C2 */
switch (config) {
case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
/* PTA to HDMI */
pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
pinmux_tristate_disable(PINGRP_DDC);
pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
pinmux_tristate_disable(PMUX_PINGRP_DDC);
break;
case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
/* set DDC_SEL to RSVDx (RSVD2 works for now) */
pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
pinmux_tristate_disable(PINGRP_PTA);
pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
pinmux_tristate_disable(PMUX_PINGRP_PTA);
bad_config = 0;
break;
}
@ -131,50 +131,50 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_I2C3: /* I2C3 */
/* support pinmux_config of 0 for now */
if (config == FUNCMUX_I2C3_DTF) {
pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
pinmux_tristate_disable(PINGRP_DTF);
pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
pinmux_tristate_disable(PMUX_PINGRP_DTF);
}
break;
case PERIPH_ID_SDMMC1:
if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PINGRP_SDIO1);
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
}
break;
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
pinmux_tristate_disable(PINGRP_DTA);
pinmux_tristate_disable(PINGRP_DTD);
pinmux_tristate_disable(PMUX_PINGRP_DTA);
pinmux_tristate_disable(PMUX_PINGRP_DTD);
}
break;
case PERIPH_ID_SDMMC3:
switch (config) {
case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
pinmux_tristate_disable(PINGRP_SLXA);
pinmux_tristate_disable(PINGRP_SLXC);
pinmux_tristate_disable(PINGRP_SLXD);
pinmux_tristate_disable(PINGRP_SLXK);
pinmux_tristate_disable(PMUX_PINGRP_SLXA);
pinmux_tristate_disable(PMUX_PINGRP_SLXC);
pinmux_tristate_disable(PMUX_PINGRP_SLXD);
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
/* fall through */
case FUNCMUX_SDMMC3_SDB_4BIT:
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
pinmux_tristate_disable(PINGRP_SDB);
pinmux_tristate_disable(PINGRP_SDC);
pinmux_tristate_disable(PINGRP_SDD);
pinmux_tristate_disable(PMUX_PINGRP_SDB);
pinmux_tristate_disable(PMUX_PINGRP_SDC);
pinmux_tristate_disable(PMUX_PINGRP_SDD);
bad_config = 0;
break;
}
@ -183,24 +183,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_SDMMC4:
switch (config) {
case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATC);
pinmux_tristate_disable(PINGRP_ATD);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
pinmux_tristate_disable(PMUX_PINGRP_ATD);
break;
case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_GME);
pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PMUX_PINGRP_GME);
/* fall through */
case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATB);
pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PMUX_PINGRP_ATB);
pinmux_tristate_disable(PMUX_PINGRP_GMA);
bad_config = 0;
break;
}
@ -208,9 +208,10 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_KBC:
if (config == FUNCMUX_DEFAULT) {
enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
PINGRP_KBCF};
enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
PMUX_PINGRP_KBCF};
int i;
for (i = 0; i < ARRAY_SIZE(grp); i++) {
@ -223,44 +224,44 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_USB2:
if (config == FUNCMUX_USB2_ULPI) {
pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
pinmux_tristate_disable(PINGRP_UAA);
pinmux_tristate_disable(PINGRP_UAB);
pinmux_tristate_disable(PINGRP_UDA);
pinmux_tristate_disable(PMUX_PINGRP_UAA);
pinmux_tristate_disable(PMUX_PINGRP_UAB);
pinmux_tristate_disable(PMUX_PINGRP_UDA);
}
break;
case PERIPH_ID_SPI1:
if (config == FUNCMUX_SPI1_GMC_GMD) {
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_tristate_disable(PINGRP_GMC);
pinmux_tristate_disable(PINGRP_GMD);
pinmux_tristate_disable(PMUX_PINGRP_GMC);
pinmux_tristate_disable(PMUX_PINGRP_GMD);
}
break;
case PERIPH_ID_NDFLASH:
switch (config) {
case FUNCMUX_NDFLASH_ATC:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_ATC);
pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
break;
case FUNCMUX_NDFLASH_KBC_8_BIT:
pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_KBCA);
pinmux_tristate_disable(PINGRP_KBCC);
pinmux_tristate_disable(PINGRP_KBCD);
pinmux_tristate_disable(PINGRP_KBCE);
pinmux_tristate_disable(PINGRP_KBCF);
pinmux_tristate_disable(PMUX_PINGRP_KBCA);
pinmux_tristate_disable(PMUX_PINGRP_KBCC);
pinmux_tristate_disable(PMUX_PINGRP_KBCD);
pinmux_tristate_disable(PMUX_PINGRP_KBCE);
pinmux_tristate_disable(PMUX_PINGRP_KBCF);
bad_config = 0;
break;
@ -270,13 +271,13 @@ int funcmux_select(enum periph_id id, int config)
if (config == FUNCMUX_DEFAULT) {
int i;
for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
pinmux_set_func(i, PMUX_FUNC_DISPA);
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
}
pinmux_config_table(disp1_default,
ARRAY_SIZE(disp1_default));
pinmux_config_pingrp_table(disp1_default,
ARRAY_SIZE(disp1_default));
}
break;

394
arch/arm/cpu/tegra20-common/pinmux.c
View file

@ -8,10 +8,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
/*
* This defines the order of the pin mux control bits in the registers. For
* some reason there is no correspendence between the tristate, pin mux and
@ -256,302 +254,172 @@ enum pmux_pullid {
PUCTL_NONE = -1
};
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id;
};
/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
/* Mask value for a tristate (within TRISTATE_REG(id)) */
#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
/* Converts a PUCTL id to a shift position */
#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
/* Converts a MUXCTL id to a shift position */
#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
/* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
{ \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
.func_safe = PMUX_FUNC_ ## f_safe, \
.ctl_id = mux, \
.pull_id = pupd \
}
/* A normal pin group where the mux name and pull-up name match */
#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
#define PIN(pingrp, f0, f1, f2, f3) \
PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
/* A pin group where the pull-up name doesn't have a 1-1 mapping */
#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
MUXCTL_ ## pg_name, PUCTL_ ## pupd)
#define PINP(pingrp, f0, f1, f2, f3, pupd) \
PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
/* A pin group number which is not used */
#define PIN_RESERVED \
PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
PLLC_OUT1),
PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
#define DRVGRP(drvgrp) \
PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
static const struct pmux_pingrp_desc tegra20_pingroups[] = {
PIN(ATA, IDE, NAND, GMI, RSVD4),
PIN(ATB, IDE, NAND, GMI, SDIO4),
PIN(ATC, IDE, NAND, GMI, SDIO4),
PIN(ATD, IDE, NAND, GMI, SDIO4),
PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
GPSLXAU),
PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
PIN(DAP2, DAP2, TWC, RSVD3, GMI),
PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
PIN(DTB, RSVD1, RSVD2, VI, SPI1),
PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
PIN(DTE, RSVD1, RSVD2, VI, SPI1),
PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
PIN(IRTX, UARTA, UARTB, GMI, SPI4),
PIN(IRRX, UARTA, UARTB, GMI, SPI4),
PIN(KBCB, KBC, NAND, SDIO2, MIO),
PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
PIN(PTA, I2C2, HDMI, GMI, RSVD4),
PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
PIN(KBCE, KBC, NAND, OWR, RSVD4),
PIN(KBCF, KBC, NAND, TRACE, MIO),
PIN(GMA, UARTE, SPI3, GMI, SDIO4),
PIN(GMC, UARTD, SPI4, GMI, SFLASH),
PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
PIN(GME, RSVD1, DAP5, GMI, SDIO4),
PIN(SDC, PWM, TWC, SDIO3, SPI3),
PIN(SDD, UARTA, PWM, SDIO3, SPI3),
PIN_RESERVED,
PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
PIN(SPIA, SPI1, SPI2, SPI3, GMI),
PIN(SPIB, SPI1, SPI2, SPI3, GMI),
PIN(SPIC, SPI1, SPI2, SPI3, GMI),
PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
PIN(UCB, UARTC, PWM, GMI, RSVD4),
PIN_RESERVED,
PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
PIN(ATE, IDE, NAND, GMI, RSVD4),
PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
PIN_RESERVED,
PIN_RESERVED,
PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
PIN(GMB, IDE, NAND, GMI, GMI_INT),
PIN(GMD, RSVD1, NAND, GMI, SFLASH),
PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
/* 64 */
PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
/* 96 */
PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PIN_RESERVED,
PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
PIN(KBCD, KBC, NAND, SDIO2, MIO),
PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
PIN(DTF, I2C3, RSVD2, VI, RSVD4),
PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
/* these pin groups only have pullup and pull down control */
PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
DRVGRP(CK32),
DRVGRP(DDRC),
DRVGRP(PMCA),
DRVGRP(PMCB),
DRVGRP(PMCC),
DRVGRP(PMCD),
DRVGRP(PMCE),
DRVGRP(XM2C),
DRVGRP(XM2D),
};
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
u32 reg;
reg = readl(tri);
if (enable)
reg |= TRISTATE_MASK(pin);
else
reg &= ~TRISTATE_MASK(pin);
writel(reg, tri);
}
void pinmux_tristate_enable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 1);
}
void pinmux_tristate_disable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 0);
}
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
u32 mask_bit;
u32 reg;
mask_bit = PULL_SHIFT(pull_id);
reg = readl(pull);
reg &= ~(0x3 << mask_bit);
reg |= pupd << mask_bit;
writel(reg, pull);
}
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
u32 mask_bit;
int i, mux = -1;
u32 reg;
assert(pmux_func_isvalid(func));
/* Handle special values */
if (func >= PMUX_FUNC_RSVD1) {
mux = (func - PMUX_FUNC_RSVD1) & 0x3;
} else {
/* Search for the appropriate function */
for (i = 0; i < 4; i++) {
if (tegra_soc_pingroups[pin].funcs[i] == func) {
mux = i;
break;
}
}
}
assert(mux != -1);
mask_bit = MUXCTL_SHIFT(mux_id);
reg = readl(muxctl);
reg &= ~(0x3 << mask_bit);
reg |= mux << mask_bit;
writel(reg, muxctl);
}
void pinmux_config_pingroup(const struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
pinmux_set_tristate(pin, config->tristate);
}
void pinmux_config_table(const struct pingroup_config *config, int len)
{
int i;
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;

8
arch/arm/cpu/tegra20-common/warmboot.c
View file

@ -15,6 +15,7 @@
#include <asm/arch/sdram_param.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/fuse.h>
@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void)
{
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void)
union fbio_spare_reg fbio_spare;
/* get ram code that is used as index to array sdram_params in BCT */
ram_code = (readl(&pmt->pmt_strap_opt_a) >>
STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
ram_code = (readl(&apb_misc->strapping_opt_a) >>
STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
memcpy(&sdram,
(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
sizeof(sdram));

6
arch/arm/cpu/tegra20-common/warmboot_avp.c
View file

@ -12,6 +12,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/warmboot.h>
@ -21,7 +22,8 @@
void wb_start(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
@ -33,7 +35,7 @@ void wb_start(void)
u32 reg;
/* enable JTAG & TBE */
writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */
asm volatile (

20
arch/arm/cpu/tegra30-common/funcmux.c
View file

@ -29,14 +29,18 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_ULPI:
pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_ULPI_DATA0);
pinmux_tristate_disable(PINGRP_ULPI_DATA1);
pinmux_tristate_disable(PINGRP_ULPI_DATA2);
pinmux_tristate_disable(PINGRP_ULPI_DATA3);
pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
break;
}
break;

952
arch/arm/cpu/tegra30-common/pinmux.c
View file

@ -1,694 +1,276 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra30 pin multiplexing functions */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
#define PIN(pin, f0, f1, f2, f3) \
{ \
.funcs = { \
PMUX_FUNC_##f0, \
PMUX_FUNC_##f1, \
PMUX_FUNC_##f2, \
PMUX_FUNC_##f3, \
}, \
}
#define PIN_RESERVED {}
static const struct pmux_pingrp_desc tegra30_pingroups[] = {
/* pin, f0, f1, f2, f3 */
/* Offset 0x3000 */
PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI),
PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI),
PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI),
PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI),
PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB),
PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB),
PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB),
PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB),
PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
PIN(PV2, OWR, RSVD2, RSVD3, RSVD4),
PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP),
PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4),
PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP),
PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP),
PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4),
PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP),
PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP),
PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4),
PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4),
PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4),
PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4),
PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4),
PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4),
PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4),
PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4),
PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3),
PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4),
PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4),
PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4),
PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4),
PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4),
PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4),
PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4),
PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4),
PIN(PU0, OWR, UARTA, GMI, RSVD4),
PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
PIN(PU3, PWM0, UARTA, GMI, RSVD4),
PIN(PU4, PWM1, UARTA, GMI, RSVD4),
PIN(PU5, PWM2, UARTA, GMI, RSVD4),
PIN(PU6, PWM3, UARTA, GMI, RSVD4),
PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4),
PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4),
PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4),
PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4),
PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA),
PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT),
PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4),
PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4),
PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4),
PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4),
PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT),
PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV),
PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV),
PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4),
PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4),
PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4),
PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4),
PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4),
PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4),
PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4),
PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4),
PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4),
PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4),
PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4),
PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4),
PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4),
PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4),
PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4),
PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4),
PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4),
PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4),
PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4),
PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4),
PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4),
PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4),
PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4),
PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4),
PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4),
PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4),
PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4),
PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4),
PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4),
PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID),
PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4),
PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR),
PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO),
PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO),
PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST),
PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST),
PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4),
PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4),
PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4),
PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4),
PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO),
PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO),
PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4),
PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4),
PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
PIN(OWR, OWR, CEC, RSVD3, RSVD4),
PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2),
PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2),
PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2),
PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2),
PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4),
PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2),
PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2),
PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI),
PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI),
PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI),
PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI),
PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI),
PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI),
PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI),
PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI),
PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4),
PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1),
PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1),
PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3),
PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2),
PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3),
PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3),
PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3),
PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3),
PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2),
PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2),
PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2),
PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2),
PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
};
#define PMUX_MUXCTL_SHIFT 0
#define PMUX_PULL_SHIFT 2
#define PMUX_TRISTATE_SHIFT 4
#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
#define PMUX_IO_SHIFT 5
#define PMUX_OD_SHIFT 6
#define PMUX_LOCK_SHIFT 7
#define PMUX_IO_RESET_SHIFT 8
#define PGRP_HSM_SHIFT 2
#define PGRP_SCHMT_SHIFT 3
#define PGRP_LPMD_SHIFT 4
#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
#define PGRP_DRVDN_SHIFT 12
#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
#define PGRP_DRVUP_SHIFT 20
#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
#define PGRP_SLWR_SHIFT 28
#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
#define PGRP_SLWF_SHIFT 30
#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
.func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
/* Input and output pins */
#define PINI(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
PINI(VI_MCLK, VI, VI, VI, VI, VI),
PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
};
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
reg = readl(tri);
if (enable)
reg |= PMUX_TRISTATE_MASK;
else
reg &= ~PMUX_TRISTATE_MASK;
writel(reg, tri);
}
void pinmux_tristate_enable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 1);
}
void pinmux_tristate_disable(enum pmux_pingrp pin)
{
pinmux_set_tristate(pin, 0);
}
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pull = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
reg = readl(pull);
reg &= ~(0x3 << PMUX_PULL_SHIFT);
reg |= (pupd << PMUX_PULL_SHIFT);
writel(reg, pull);
}
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *muxctl = &pmt->pmt_ctl[pin];
int i, mux = -1;
u32 reg;
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
/* Handle special values */
if (func == PMUX_FUNC_SAFE)
func = tegra_soc_pingroups[pin].func_safe;
if (func & PMUX_FUNC_RSVD1) {
mux = func & 0x3;
} else {
/* Search for the appropriate function */
for (i = 0; i < 4; i++) {
if (tegra_soc_pingroups[pin].funcs[i] == func) {
mux = i;
break;
}
}
}
assert(mux != -1);
reg = readl(muxctl);
reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
reg |= (mux << PMUX_MUXCTL_SHIFT);
writel(reg, muxctl);
}
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_io = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and io */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
reg = readl(pin_io);
reg &= ~(0x1 << PMUX_IO_SHIFT);
reg |= (io & 0x1) << PMUX_IO_SHIFT;
writel(reg, pin_io);
}
static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_lock = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and lock */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
if (lock == PMUX_PIN_LOCK_DEFAULT)
return 0;
reg = readl(pin_lock);
reg &= ~(0x1 << PMUX_LOCK_SHIFT);
if (lock == PMUX_PIN_LOCK_ENABLE)
reg |= (0x1 << PMUX_LOCK_SHIFT);
else {
/* lock == DISABLE, which isn't possible */
printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
__func__, lock);
}
writel(reg, pin_lock);
return 0;
}
static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_od = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and od */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_od_isvalid(od));
if (od == PMUX_PIN_OD_DEFAULT)
return 0;
reg = readl(pin_od);
reg &= ~(0x1 << PMUX_OD_SHIFT);
if (od == PMUX_PIN_OD_ENABLE)
reg |= (0x1 << PMUX_OD_SHIFT);
writel(reg, pin_od);
return 0;
}
static int pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_ioreset = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and ioreset */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_ioreset_isvalid(ioreset));
if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
return 0;
reg = readl(pin_ioreset);
reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
reg |= (0x1 << PMUX_IO_RESET_SHIFT);
writel(reg, pin_ioreset);
return 0;
}
void pinmux_config_pingroup(struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
pinmux_set_tristate(pin, config->tristate);
pinmux_set_io(pin, config->io);
pinmux_set_lock(pin, config->lock);
pinmux_set_od(pin, config->od);
pinmux_set_ioreset(pin, config->ioreset);
}
void pinmux_config_table(struct pingroup_config *config, int len)
{
int i;
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
int slwf)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwf = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwf */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwf));
/* NONE means unspecified/do not change/use POR value */
if (slwf == PGRP_SLWF_NONE)
return 0;
reg = readl(pad_slwf);
reg &= ~PGRP_SLWF_MASK;
reg |= (slwf << PGRP_SLWF_SHIFT);
writel(reg, pad_slwf);
return 0;
}
static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwr = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwr */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwr));
/* NONE means unspecified/do not change/use POR value */
if (slwr == PGRP_SLWR_NONE)
return 0;
reg = readl(pad_slwr);
reg &= ~PGRP_SLWR_MASK;
reg |= (slwr << PGRP_SLWR_SHIFT);
writel(reg, pad_slwr);
return 0;
}
static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvup = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvup */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvup));
/* NONE means unspecified/do not change/use POR value */
if (drvup == PGRP_DRVUP_NONE)
return 0;
reg = readl(pad_drvup);
reg &= ~PGRP_DRVUP_MASK;
reg |= (drvup << PGRP_DRVUP_SHIFT);
writel(reg, pad_drvup);
return 0;
}
static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvdn = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvdn */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvdn));
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PGRP_DRVDN_NONE)
return 0;
reg = readl(pad_drvdn);
reg &= ~PGRP_DRVDN_MASK;
reg |= (drvdn << PGRP_DRVDN_SHIFT);
writel(reg, pad_drvdn);
return 0;
}
static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_lpmd = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad and lpmd value */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_lpmd_isvalid(lpmd));
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PGRP_LPMD_NONE)
return 0;
reg = readl(pad_lpmd);
reg &= ~PGRP_LPMD_MASK;
reg |= (lpmd << PGRP_LPMD_SHIFT);
writel(reg, pad_lpmd);
return 0;
}
static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_schmt = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
reg = readl(pad_schmt);
reg &= ~(1 << PGRP_SCHMT_SHIFT);
if (schmt == PGRP_SCHMT_ENABLE)
reg |= (0x1 << PGRP_SCHMT_SHIFT);
writel(reg, pad_schmt);
return 0;
}
static int padgrp_set_hsm(enum pdrive_pingrp pad,
enum pgrp_hsm hsm)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_hsm = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
reg = readl(pad_hsm);
reg &= ~(1 << PGRP_HSM_SHIFT);
if (hsm == PGRP_HSM_ENABLE)
reg |= (0x1 << PGRP_HSM_SHIFT);
writel(reg, pad_hsm);
return 0;
}
void padctrl_config_pingroup(struct padctrl_config *config)
{
enum pdrive_pingrp pad = config->padgrp;
padgrp_set_drvup_slwf(pad, config->slwf);
padgrp_set_drvdn_slwr(pad, config->slwr);
padgrp_set_drvup(pad, config->drvup);
padgrp_set_drvdn(pad, config->drvdn);
padgrp_set_lpmd(pad, config->lpmd);
padgrp_set_schmt(pad, config->schmt);
padgrp_set_hsm(pad, config->hsm);
}
void padgrp_config_table(struct padctrl_config *config, int len)
{
int i;
for (i = 0; i < len; i++)
padctrl_config_pingroup(&config[i]);
}
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;

1
arch/arm/dts/Makefile
View file

@ -22,6 +22,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-cardhu.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \

84
arch/arm/dts/tegra124-jetson-tk1.dts Normal file
View file

@ -0,0 +1,84 @@
/dts-v1/;
#include "tegra124.dtsi"
/ {
model = "NVIDIA Jetson TK1";
compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
aliases {
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
sdhci0 = "/sdhci@700b0600";
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d008000";
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000d100 {
status = "okay";
clock-frequency = <400000>;
};
spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
};
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
power-gpios = <&gpio 136 0>; /* gpio PR0 */
bus-width = <4>;
};
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
};
};

3
arch/arm/include/asm/arch-davinci/da850_lowlevel.h
View file

@ -26,11 +26,8 @@ extern const int lpsc_size;
#define dv_maskbits(addr, val) \
writel((readl(addr) & val), addr)
void da850_waitloop(unsigned long loopcnt);
int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
void da850_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state);
int da850_ddr_setup(void);
void da850_psc_init(void);
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value);

71
arch/arm/include/asm/arch-davinci/i2c_defs.h
View file

@ -1,16 +1,13 @@
/*
* (C) Copyright 2004
* (C) Copyright 2004-2014
* Texas Instruments, <www.ti.com>
*
* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DAVINCI_I2C_H_
#define _DAVINCI_I2C_H_
#define I2C_WRITE 0
#define I2C_READ 1
#ifndef _I2C_DEFS_H_
#define _I2C_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
@ -18,66 +15,4 @@
#define I2C_BASE 0x01c22000
#endif
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
#define I2C_STAT (I2C_BASE + 0x08)
#define I2C_SCLL (I2C_BASE + 0x0c)
#define I2C_SCLH (I2C_BASE + 0x10)
#define I2C_CNT (I2C_BASE + 0x14)
#define I2C_DRR (I2C_BASE + 0x18)
#define I2C_SA (I2C_BASE + 0x1c)
#define I2C_DXR (I2C_BASE + 0x20)
#define I2C_CON (I2C_BASE + 0x24)
#define I2C_IV (I2C_BASE + 0x28)
#define I2C_PSC (I2C_BASE + 0x30)
/* I2C masks */
/* I2C Interrupt Enable Register (I2C_IE): */
#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Status Register (I2C_STAT): */
#define I2C_STAT_BB (1 << 12) /* Bus busy */
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
#define I2C_STAT_AAS (1 << 9) /* Address as slave */
#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Interrupt Code Register (I2C_INTCODE): */
#define I2C_INTCODE_MASK 7
#define I2C_INTCODE_NONE 0
#define I2C_INTCODE_AL 1 /* Arbitration lost */
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
#define I2C_INTCODE_ARDY 3 /* Register access ready */
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
#define I2C_INTCODE_SCD 6 /* Stop condition detect */
/* I2C Configuration Register (I2C_CON): */
#define I2C_CON_EN (1 << 5) /* I2C module enable */
#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
#define I2C_CON_MST (1 << 10) /* Master/slave mode */
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
#endif

109
arch/arm/include/asm/arch-keystone/clock-k2hk.h Normal file
View file

@ -0,0 +1,109 @@
/*
* K2HK: Clock management APIs
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
#include <asm/arch/hardware.h>
#ifndef __ASSEMBLY__
enum ext_clk_e {
sys_clk,
alt_core_clk,
pa_clk,
tetris_clk,
ddr3a_clk,
ddr3b_clk,
mcm_clk,
pcie_clk,
sgmii_srio_clk,
xgmii_clk,
usb_clk,
rp1_clk,
ext_clk_count /* number of external clocks */
};
extern unsigned int external_clk[ext_clk_count];
enum clk_e {
core_pll_clk,
pass_pll_clk,
tetris_pll_clk,
ddr3a_pll_clk,
ddr3b_pll_clk,
sys_clk0_clk,
sys_clk0_1_clk,
sys_clk0_2_clk,
sys_clk0_3_clk,
sys_clk0_4_clk,
sys_clk0_6_clk,
sys_clk0_8_clk,
sys_clk0_12_clk,
sys_clk0_24_clk,
sys_clk1_clk,
sys_clk1_3_clk,
sys_clk1_4_clk,
sys_clk1_6_clk,
sys_clk1_12_clk,
sys_clk2_clk,
sys_clk3_clk
};
#define K2HK_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
TETRIS_PLL,
DDR3A_PLL,
DDR3B_PLL,
};
#define MAIN_PLL CORE_PLL
/* PLL configuration data */
struct pll_init_data {
int pll;
int pll_m; /* PLL Multiplier */
int pll_d; /* PLL divider */
int pll_od; /* PLL output divider */
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
#endif
#endif

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/*
* keystone2: common clock header file
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/clock-k2hk.h>
#endif
#endif

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/*
* keystone2: common pll clock definitions
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CLOCK_DEFS_H_
#define _CLOCK_DEFS_H_
#include <asm/arch/hardware.h>
#define BIT(x) (1 << (x))
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */
u32 ocsel; /* 04 */
u32 secctl; /* 08 */
u32 resv0;
u32 mult; /* 10 */
u32 prediv; /* 14 */
u32 div1; /* 18 */
u32 div2; /* 1c */
u32 div3; /* 20 */
u32 oscdiv1; /* 24 */
u32 resv1; /* 28 */
u32 bpdiv; /* 2c */
u32 wakeup; /* 30 */
u32 resv2;
u32 cmd; /* 38 */
u32 stat; /* 3c */
u32 alnctl; /* 40 */
u32 dchange; /* 44 */
u32 cken; /* 48 */
u32 ckstat; /* 4c */
u32 systat; /* 50 */
u32 ckctl; /* 54 */
u32 resv3[2];
u32 div4; /* 60 */
u32 div5; /* 64 */
u32 div6; /* 68 */
u32 div7; /* 6c */
u32 div8; /* 70 */
u32 div9; /* 74 */
u32 div10; /* 78 */
u32 div11; /* 7c */
u32 div12; /* 80 */
};
static struct pllctl_regs *pllctl_regs[] = {
(struct pllctl_regs *)(CLOCK_BASE + 0x100)
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
#define pllctl_reg_rmw(pll, reg, mask, val) \
pllctl_reg_write(pll, reg, \
(pllctl_reg_read(pll, reg) & ~(mask)) | val)
#define pllctl_reg_setbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, 0, mask)
#define pllctl_reg_clrbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, mask, 0)
#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
/* PLLCTL Bits */
#define PLLCTL_BYPASS BIT(23)
#define PLL_PLLRST BIT(14)
#define PLLCTL_PAPLL BIT(13)
#define PLLCTL_CLKMODE BIT(8)
#define PLLCTL_PLLSELB BIT(7)
#define PLLCTL_ENSAT BIT(6)
#define PLLCTL_PLLENSRC BIT(5)
#define PLLCTL_PLLDIS BIT(4)
#define PLLCTL_PLLRST BIT(3)
#define PLLCTL_PLLPWRDN BIT(1)
#define PLLCTL_PLLEN BIT(0)
#define PLLSTAT_GO BIT(0)
#define MAIN_ENSAT_OFFSET 6
#define PLLDIV_ENABLE BIT(15)
#define PLL_DIV_MASK 0x3f
#define PLL_MULT_MASK 0x1fff
#define PLL_MULT_SHIFT 6
#define PLLM_MULT_HI_MASK 0x7f
#define PLLM_MULT_HI_SHIFT 12
#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
#define PLLM_MULT_LO_MASK 0x3f
#define PLL_CLKOD_MASK 0xf
#define PLL_CLKOD_SHIFT 19
#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
#define PLL_BWADJ_LO_MASK 0xff
#define PLL_BWADJ_LO_SHIFT 24
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
#endif /* _CLOCK_DEFS_H_ */

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/*
* emac definitions for keystone2 devices
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EMAC_DEFS_H_
#define _EMAC_DEFS_H_
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define DEVICE_REG32_R(a) readl(a)
#define DEVICE_REG32_W(a, v) writel(v, a)
#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
#define KEYSTONE2_EMAC_GIG_ENABLE
#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
#ifdef CONFIG_SOC_K2HK
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
#endif
/* MII Status Register */
#define MII_STATUS_REG 1
#define MII_STATUS_LINK_MASK (0x4)
/* Marvell 88E1111 PHY ID */
#define PHY_MARVELL_88E1111 (0x01410cc0)
#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#define MDIO_CONTROL_FAULT (0x80000)
#define MDIO_USERACCESS0_GO (0x80000000)
#define MDIO_USERACCESS0_WRITE_READ (0x0)
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
#define MDIO_USERACCESS0_ACK (0x20000000)
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
struct mac_sl_cfg {
u_int32_t max_rx_len; /* Maximum receive packet length. */
u_int32_t ctl; /* Control bitfield */
};
/*
* Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
*/
#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
#define GMACSL_ENABLE_GIG_MODE (1 << 7)
#define GMACSL_TX_ENABLE_PACE (1 << 6)
#define GMACSL_ENABLE (1 << 5)
#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
#define GMACSL_ENABLE_LOOPBACK (1 << 1)
#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
/*
* DEFINTITION: function return values
*/
#define GMACSL_RET_OK 0
#define GMACSL_RET_INVALID_PORT -1
#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
/* Register offsets */
#define CPGMACSL_REG_ID 0x00
#define CPGMACSL_REG_CTL 0x04
#define CPGMACSL_REG_STATUS 0x08
#define CPGMACSL_REG_RESET 0x0c
#define CPGMACSL_REG_MAXLEN 0x10
#define CPGMACSL_REG_BOFF 0x14
#define CPGMACSL_REG_RX_PAUSE 0x18
#define CPGMACSL_REG_TX_PAURSE 0x1c
#define CPGMACSL_REG_EM_CTL 0x20
#define CPGMACSL_REG_PRI 0x24
/* Soft reset register values */
#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
/* Maxlen register values */
#define CPGMAC_REG_MAXLEN_LEN 0x3fff
/* Control bitfields */
#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
#define CPSW_CTL_P0_ENABLE (1 << 2)
#define CPSW_CTL_VLAN_AWARE (1 << 1)
#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
#define DEVICE_CPSW_BASE (0x02090800)
#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
#define SWITCH_MAX_PKT_SIZE 9000
/* Register offsets */
#define CPSW_REG_CTL 0x004
#define CPSW_REG_STAT_PORT_EN 0x00c
#define CPSW_REG_MAXLEN 0x040
#define CPSW_REG_ALE_CONTROL 0x608
#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
/* Register values */
#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
#define SGMII_REG_STATUS_LOCK BIT(4)
#define SGMII_REG_STATUS_LINK BIT(0)
#define SGMII_REG_STATUS_AUTONEG BIT(2)
#define SGMII_REG_CONTROL_AUTONEG BIT(0)
#define SGMII_REG_CONTROL_MASTER BIT(5)
#define SGMII_REG_MR_ADV_ENABLE BIT(0)
#define SGMII_REG_MR_ADV_LINK BIT(15)
#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
#define SGMII_LINK_MAC_MAC_AUTONEG 0
#define SGMII_LINK_MAC_PHY 1
#define SGMII_LINK_MAC_MAC_FORCED 2
#define SGMII_LINK_MAC_FIBER 3
#define SGMII_LINK_MAC_PHY_FORCED 4
#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
KS2_PASS_BASE + 0x00090200, \
KS2_PASS_BASE + 0x00090400, \
KS2_PASS_BASE + 0x00090500}
#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
/*
* SGMII registers
*/
#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
#define DEVICE_N_GMACSL_PORTS 4
#define DEVICE_EMACSL_RESET_POLL_COUNT 100
#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
#ifdef CONFIG_SOC_K2HK
#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
#endif
#define hw_config_streaming_switch() \
DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
/* EMAC MDIO Registers Structure */
struct mdio_regs {
dv_reg version;
dv_reg control;
dv_reg alive;
dv_reg link;
dv_reg linkintraw;
dv_reg linkintmasked;
u_int8_t rsvd0[8];
dv_reg userintraw;
dv_reg userintmasked;
dv_reg userintmaskset;
dv_reg userintmaskclear;
u_int8_t rsvd1[80];
dv_reg useraccess0;
dv_reg userphysel0;
dv_reg useraccess1;
dv_reg userphysel1;
};
/* Ethernet MAC Registers Structure */
struct emac_regs {
dv_reg idver;
dv_reg maccontrol;
dv_reg macstatus;
dv_reg soft_reset;
dv_reg rx_maxlen;
u32 rsvd0;
dv_reg rx_pause;
dv_reg tx_pause;
dv_reg emcontrol;
dv_reg pri_map;
u32 rsvd1[6];
};
#define SGMII_ACCESS(port, reg) \
*((volatile unsigned int *)(sgmiis[port] + reg))
struct eth_priv_t {
char int_name[32];
int rx_flow;
int phy_addr;
int slave_port;
int sgmii_link_type;
};
extern struct eth_priv_t eth_priv_cfg[];
int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
void sgmii_serdes_setup_156p25mhz(void);
void sgmii_serdes_shutdown(void);
#endif /* _EMAC_DEFS_H_ */

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/*
* emif definitions to re-use davinci emif driver on Keystone2
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EMIF_DEFS_H_
#define _EMIF_DEFS_H_
#include <asm/arch/hardware.h>
struct davinci_emif_regs {
uint32_t ercsr;
uint32_t awccr;
uint32_t sdbcr;
uint32_t sdrcr;
uint32_t abncr[4];
uint32_t sdtimr;
uint32_t ddrsr;
uint32_t ddrphycr;
uint32_t ddrphysr;
uint32_t totar;
uint32_t totactr;
uint32_t ddrphyid_rev;
uint32_t sdsretr;
uint32_t eirr;
uint32_t eimr;
uint32_t eimsr;
uint32_t eimcr;
uint32_t ioctrlr;
uint32_t iostatr;
uint32_t rsvd0;
uint32_t one_nand_cr;
uint32_t nandfcr;
uint32_t nandfsr;
uint32_t rsvd1[2];
uint32_t nandfecc[4];
uint32_t rsvd2[15];
uint32_t nand4biteccload;
uint32_t nand4bitecc[4];
uint32_t nanderradd1;
uint32_t nanderradd2;
uint32_t nanderrval1;
uint32_t nanderrval2;
};
#define davinci_emif_regs \
((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
#define DAVINCI_ABCR_TA(n) ((n) << 2)
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
#endif

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/*
* K2HK: SoC definitions
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
#define K2HK_PLL_CNTRL_BASE 0x02310000
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
#define KS2_RSTCTRL_KEY 0x5a69
#define KS2_RSTCTRL_MASK 0xffff0000
#define KS2_RSTCTRL_SWRST 0xfffe0000
#define K2HK_PSC_BASE 0x02350000
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
#define ARM_PLL_EN BIT(13)
#define K2HK_SPI0_BASE 0x21000400
#define K2HK_SPI1_BASE 0x21000600
#define K2HK_SPI2_BASE 0x21000800
#define K2HK_SPI_BASE K2HK_SPI0_BASE
/* Chip configuration unlock codes and registers */
#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
#define KEYSTONE_KICK0_MAGIC 0x83e70b13
#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
/* PA SS Registers */
#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
/* Power and Sleep Controller (PSC) Domains */
#define K2HK_LPSC_MOD 0
#define K2HK_LPSC_DUMMY1 1
#define K2HK_LPSC_USB 2
#define K2HK_LPSC_EMIF25_SPI 3
#define K2HK_LPSC_TSIP 4
#define K2HK_LPSC_DEBUGSS_TRC 5
#define K2HK_LPSC_TETB_TRC 6
#define K2HK_LPSC_PKTPROC 7
#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
#define K2HK_LPSC_SGMII 8
#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
#define K2HK_LPSC_CRYPTO 9
#define K2HK_LPSC_PCIE 10
#define K2HK_LPSC_SRIO 11
#define K2HK_LPSC_VUSR0 12
#define K2HK_LPSC_CHIP_SRSS 13
#define K2HK_LPSC_MSMC 14
#define K2HK_LPSC_GEM_0 15
#define K2HK_LPSC_GEM_1 16
#define K2HK_LPSC_GEM_2 17
#define K2HK_LPSC_GEM_3 18
#define K2HK_LPSC_GEM_4 19
#define K2HK_LPSC_GEM_5 20
#define K2HK_LPSC_GEM_6 21
#define K2HK_LPSC_GEM_7 22
#define K2HK_LPSC_EMIF4F_DDR3A 23
#define K2HK_LPSC_EMIF4F_DDR3B 24
#define K2HK_LPSC_TAC 25
#define K2HK_LPSC_RAC 26
#define K2HK_LPSC_RAC_1 27
#define K2HK_LPSC_FFTC_A 28
#define K2HK_LPSC_FFTC_B 29
#define K2HK_LPSC_FFTC_C 30
#define K2HK_LPSC_FFTC_D 31
#define K2HK_LPSC_FFTC_E 32
#define K2HK_LPSC_FFTC_F 33
#define K2HK_LPSC_AI2 34
#define K2HK_LPSC_TCP3D_0 35
#define K2HK_LPSC_TCP3D_1 36
#define K2HK_LPSC_TCP3D_2 37
#define K2HK_LPSC_TCP3D_3 38
#define K2HK_LPSC_VCP2X4_A 39
#define K2HK_LPSC_CP2X4_B 40
#define K2HK_LPSC_VCP2X4_C 41
#define K2HK_LPSC_VCP2X4_D 42
#define K2HK_LPSC_VCP2X4_E 43
#define K2HK_LPSC_VCP2X4_F 44
#define K2HK_LPSC_VCP2X4_G 45
#define K2HK_LPSC_VCP2X4_H 46
#define K2HK_LPSC_BCP 47
#define K2HK_LPSC_DXB 48
#define K2HK_LPSC_VUSR1 49
#define K2HK_LPSC_XGE 50
#define K2HK_LPSC_ARM_SREFLEX 51
#define K2HK_LPSC_TETRIS 52
#define K2HK_UART0_BASE 0x02530c00
/* DDR3A definitions */
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
#define K2HK_DDR3A_DDRPHYC 0x02329000
/* DDR3B definitions */
#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
#define K2HK_DDR3B_DDRPHYC 0x02328000
/* Queue manager */
#define DEVICE_QM_MANAGER_BASE 0x02a02000
#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
#define DEVICE_QM_NUM_LINKRAMS 2
#define DEVICE_QM_NUM_MEMREGIONS 20
#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
/* MSMC control */
#define K2HK_MSMC_CTRL_BASE 0x0bc00000
#endif /* __ASM_ARCH_HARDWARE_H */

175
arch/arm/include/asm/arch-keystone/hardware.h Normal file
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@ -0,0 +1,175 @@
/*
* Keystone2: Common SoC definitions, structures etc.
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <config.h>
#ifndef __ASSEMBLY__
#include <linux/sizes.h>
#include <asm/io.h>
#define REG(addr) (*(volatile unsigned int *)(addr))
#define REG_P(addr) ((volatile unsigned int *)(addr))
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
#define ASYNC_EMIF_NUM_CS 4
#define ASYNC_EMIF_MODE_NOR 0
#define ASYNC_EMIF_MODE_NAND 1
#define ASYNC_EMIF_MODE_ONENAND 2
#define ASYNC_EMIF_PRESERVE -1
struct async_emif_config {
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
unsigned wr_setup;
unsigned wr_strobe;
unsigned wr_hold;
unsigned rd_setup;
unsigned rd_strobe;
unsigned rd_hold;
unsigned turn_around;
enum {
ASYNC_EMIF_8 = 0,
ASYNC_EMIF_16 = 1,
ASYNC_EMIF_32 = 2,
} width;
};
void init_async_emif(int num_cs, struct async_emif_config *config);
struct ddr3_phy_config {
unsigned int pllcr;
unsigned int pgcr1_mask;
unsigned int pgcr1_val;
unsigned int ptr0;
unsigned int ptr1;
unsigned int ptr2;
unsigned int ptr3;
unsigned int ptr4;
unsigned int dcr_mask;
unsigned int dcr_val;
unsigned int dtpr0;
unsigned int dtpr1;
unsigned int dtpr2;
unsigned int mr0;
unsigned int mr1;
unsigned int mr2;
unsigned int dtcr;
unsigned int pgcr2;
unsigned int zq0cr1;
unsigned int zq1cr1;
unsigned int zq2cr1;
unsigned int pir_v1;
unsigned int pir_v2;
};
struct ddr3_emif_config {
unsigned int sdcfg;
unsigned int sdtim1;
unsigned int sdtim2;
unsigned int sdtim3;
unsigned int sdtim4;
unsigned int zqcfg;
unsigned int sdrfc;
};
#endif
#define BIT(x) (1 << (x))
#define KS2_DDRPHY_PIR_OFFSET 0x04
#define KS2_DDRPHY_PGCR0_OFFSET 0x08
#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
#define KS2_DDRPHY_PGSR0_OFFSET 0x10
#define KS2_DDRPHY_PGSR1_OFFSET 0x14
#define KS2_DDRPHY_PLLCR_OFFSET 0x18
#define KS2_DDRPHY_PTR0_OFFSET 0x1C
#define KS2_DDRPHY_PTR1_OFFSET 0x20
#define KS2_DDRPHY_PTR2_OFFSET 0x24
#define KS2_DDRPHY_PTR3_OFFSET 0x28
#define KS2_DDRPHY_PTR4_OFFSET 0x2C
#define KS2_DDRPHY_DCR_OFFSET 0x44
#define KS2_DDRPHY_DTPR0_OFFSET 0x48
#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
#define KS2_DDRPHY_DTPR2_OFFSET 0x50
#define KS2_DDRPHY_MR0_OFFSET 0x54
#define KS2_DDRPHY_MR1_OFFSET 0x58
#define KS2_DDRPHY_MR2_OFFSET 0x5C
#define KS2_DDRPHY_DTCR_OFFSET 0x68
#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
#define IODDRM_MASK 0x00000180
#define ZCKSEL_MASK 0x01800000
#define CL_MASK 0x00000072
#define WR_MASK 0x00000E00
#define BL_MASK 0x00000003
#define RRMODE_MASK 0x00040000
#define UDIMM_MASK 0x20000000
#define BYTEMASK_MASK 0x0003FC00
#define MPRDQ_MASK 0x00000080
#define PDQ_MASK 0x00000070
#define NOSRA_MASK 0x08000000
#define ECC_MASK 0x00000001
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define KS2_DDR3_SDCFG_OFFSET 0x08
#define KS2_DDR3_SDRFC_OFFSET 0x10
#define KS2_DDR3_SDTIM1_OFFSET 0x18
#define KS2_DDR3_SDTIM2_OFFSET 0x1C
#define KS2_DDR3_SDTIM3_OFFSET 0x20
#define KS2_DDR3_SDTIM4_OFFSET 0x28
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb981) ? 1 : 0;
}
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
unsigned int rev = (jtag_id >> 28) & 0xf;
return rev;
}
void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
void init_ddr3(void);
void sdelay(unsigned long);
#endif
#endif /* __ASM_ARCH_HARDWARE_H */

17
arch/arm/include/asm/arch-keystone/i2c_defs.h Normal file
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@ -0,0 +1,17 @@
/*
* keystone: i2c driver definitions
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _I2C_DEFS_H_
#define _I2C_DEFS_H_
#define I2C0_BASE 0x02530000
#define I2C1_BASE 0x02530400
#define I2C2_BASE 0x02530800
#define I2C_BASE I2C0_BASE
#endif

193
arch/arm/include/asm/arch-keystone/keystone_nav.h Normal file
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@ -0,0 +1,193 @@
/*
* Multicore Navigator definitions
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _KEYSTONE_NAV_H_
#define _KEYSTONE_NAV_H_
#include <asm/arch/hardware.h>
#include <asm/io.h>
enum soc_type_t {
k2hk
};
#define QM_OK 0
#define QM_ERR -1
#define QM_DESC_TYPE_HOST 0
#define QM_DESC_PSINFO_IN_DESCR 0
#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
(QM_DESC_PSINFO_IN_DESCR << 22)
/* Packet Info */
#define QM_DESC_PINFO_EPIB 1
#define QM_DESC_PINFO_RETURN_OWN 1
#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
(QM_DESC_PINFO_RETURN_OWN << 15)
struct qm_cfg_reg {
u32 revision;
u32 __pad1;
u32 divert;
u32 link_ram_base0;
u32 link_ram_size0;
u32 link_ram_base1;
u32 link_ram_size1;
u32 link_ram_base2;
u32 starvation[0];
};
struct descr_mem_setup_reg {
u32 base_addr;
u32 start_idx;
u32 desc_reg_size;
u32 _res0;
};
struct qm_reg_queue {
u32 entry_count;
u32 byte_count;
u32 packet_size;
u32 ptr_size_thresh;
};
struct qm_config {
/* QM module addresses */
u32 stat_cfg; /* status and config */
struct qm_reg_queue *queue; /* management region */
u32 mngr_vbusm; /* management region (VBUSM) */
u32 i_lram; /* internal linking RAM */
struct qm_reg_queue *proxy;
u32 status_ram;
struct qm_cfg_reg *mngr_cfg;
/* Queue manager config region */
u32 intd_cfg; /* QMSS INTD config region */
struct descr_mem_setup_reg *desc_mem;
/* descritor memory setup region*/
u32 region_num;
u32 pdsp_cmd; /* PDSP1 command interface */
u32 pdsp_ctl; /* PDSP1 control registers */
u32 pdsp_iram;
/* QM configuration parameters */
u32 qpool_num; /* */
};
struct qm_host_desc {
u32 desc_info;
u32 tag_info;
u32 packet_info;
u32 buff_len;
u32 buff_ptr;
u32 next_bdptr;
u32 orig_buff_len;
u32 orig_buff_ptr;
u32 timestamp;
u32 swinfo[3];
u32 ps_data[20];
};
#define HDESC_NUM 256
int qm_init(void);
void qm_close(void);
void qm_push(struct qm_host_desc *hd, u32 qnum);
struct qm_host_desc *qm_pop(u32 qnum);
void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
void *buff_ptr, u32 buff_len);
struct qm_host_desc *qm_pop_from_free_pool(void);
void queue_close(u32 qnum);
/*
* DMA API
*/
#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
psloc, sopoff, qmgr, qnum) \
(((einfo & 1) << 30) | \
((psinfo & 1) << 29) | \
((rxerr & 1) << 28) | \
((desc & 3) << 26) | \
((psloc & 1) << 25) | \
((sopoff & 0x1ff) << 16) | \
((qmgr & 3) << 12) | \
((qnum & 0xfff) << 0))
#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
(((fd0qm & 3) << 28) | \
((fd0qnum & 0xfff) << 16) | \
((fd1qm & 3) << 12) | \
((fd1qnum & 0xfff) << 0))
#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
#define CPDMA_CHAN_A_TDOWN (1 << 30)
#define TDOWN_TIMEOUT_COUNT 100
struct global_ctl_regs {
u32 revision;
u32 perf_control;
u32 emulation_control;
u32 priority_control;
u32 qm_base_addr[4];
};
struct tx_chan_regs {
u32 cfg_a;
u32 cfg_b;
u32 res[6];
};
struct rx_chan_regs {
u32 cfg_a;
u32 res[7];
};
struct rx_flow_regs {
u32 control;
u32 tags;
u32 tag_sel;
u32 fdq_sel[2];
u32 thresh[3];
};
struct pktdma_cfg {
struct global_ctl_regs *global;
struct tx_chan_regs *tx_ch;
u32 tx_ch_num;
struct rx_chan_regs *rx_ch;
u32 rx_ch_num;
u32 *tx_sched;
struct rx_flow_regs *rx_flows;
u32 rx_flow_num;
u32 rx_free_q;
u32 rx_rcv_q;
u32 tx_snd_q;
u32 rx_flow; /* flow that is used for RX */
};
/*
* packet dma user allocates memory for rx buffers
* and describe it in the following structure
*/
struct rx_buff_desc {
u8 *buff_ptr;
u32 num_buffs;
u32 buff_len;
u32 rx_flow;
};
int netcp_close(void);
int netcp_init(struct rx_buff_desc *rx_buffers);
int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
void *netcp_recv(u32 **pkt, int *num_bytes);
void netcp_release_rxhd(void *hd);
#endif /* _KEYSTONE_NAV_H_ */

23
arch/arm/include/asm/arch-keystone/nand_defs.h Normal file
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@ -0,0 +1,23 @@
/*
* nand driver definitions to re-use davinci nand driver on Keystone2
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _NAND_DEFS_H_
#define _NAND_DEFS_H_
#include <asm/arch/hardware.h>
#include <linux/mtd/nand.h>
#define MASK_CLE 0x4000
#define MASK_ALE 0x2000
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
#endif

90
arch/arm/include/asm/arch-keystone/psc_defs.h Normal file
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@ -0,0 +1,90 @@
/*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PSC_DEFS_H_
#define _PSC_DEFS_H_
#include <asm/arch/hardware.h>
/*
* FILE PURPOSE: Local Power Sleep Controller definitions
*
* FILE NAME: psc_defs.h
*
* DESCRIPTION: Provides local definitions for the power saver controller
*
*/
/* Register offsets */
#define PSC_REG_PTCMD 0x120
#define PSC_REG_PSTAT 0x128
#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
#define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
#define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
(u32)1)) << ((u32)y)))
#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y)
#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \
((((u32)f) << (y)) & BOOTBITMASK(x, y))
/* PDCTL */
#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
/* PDSTAT */
#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
/* MDCFG */
#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
/* MDCTL */
#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
12, 12)
/* MDSTAT */
#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
/* PDCTL states */
#define PSC_REG_VAL_PDCTL_NEXT_ON 1
#define PSC_REG_VAL_PDCTL_NEXT_OFF 0
#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
/* MDCTL states */
#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
#define PSC_REG_VAL_MDCTL_NEXT_OFF 2
#define PSC_REG_VAL_MDCTL_NEXT_ON 3
/* MDSTAT states */
#define PSC_REG_VAL_MDSTAT_STATE_ON 3
#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
#define PSC_REG_VAL_MDSTAT_STATE_OFF 2
#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
/*
* Timeout limit on checking PTSTAT. This is the number of times the
* wait function will be called before giving up.
*/
#define PSC_PTSTAT_TIMEOUT_LIMIT 100
u32 psc_get_domain_num(u32 mod_num);
int psc_enable_module(u32 mod_num);
int psc_disable_module(u32 mod_num);
int psc_disable_domain(u32 domain_num);
#endif /* _PSC_DEFS_H_ */

12
arch/arm/include/asm/arch-keystone/spl.h Normal file
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@ -0,0 +1,12 @@
/*
* (C) Copyright 2012-2014
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define BOOT_DEVICE_SPI 2
#endif

3
arch/arm/include/asm/arch-omap3/sys_proto.h
View file

@ -8,6 +8,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <linux/mtd/omap_gpmc.h>
#include <asm/omap_common.h>
typedef struct {
u32 mtype;
@ -62,13 +63,13 @@ void secureworld_exit(void);
void try_unlock_memory(void);
u32 get_boot_type(void);
void invalidate_dcache(u32);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void dieid_num_r(void);
void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
u32 warm_reset(void);

1
arch/arm/include/asm/arch-omap4/sys_proto.h
View file

@ -31,7 +31,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);

1
arch/arm/include/asm/arch-omap5/sys_proto.h
View file

@ -32,7 +32,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_clocks_for_console(void);

2
arch/arm/include/asm/arch-tegra20/apb_misc.h → arch/arm/include/asm/arch-tegra/apb_misc.h
View file

@ -11,6 +11,8 @@
struct apb_misc_pp_ctlr {
u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
u32 reserved1[6]; /* 0x0c .. 0x20 */
u32 cfg_ctl; /* 0x24 */
};
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */

1
arch/arm/include/asm/arch-tegra/board.h
View file

@ -24,6 +24,7 @@ void gpio_early_init(void); /* overrideable GPIO config */
* an empty stub function will be called.
*/
void pinmux_init(void); /* overrideable general pinmux setup */
void pin_mux_usb(void); /* overrideable USB pinmux setup */
void pin_mux_spi(void); /* overrideable SPI pinmux setup */
void pin_mux_nand(void); /* overrideable NAND pinmux setup */

185
arch/arm/include/asm/arch-tegra/pinmux.h Normal file
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@ -0,0 +1,185 @@
/*
* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_PINMUX_H_
#define _TEGRA_PINMUX_H_
#include <asm/arch/tegra.h>
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
#ifdef TEGRA_PMX_HAS_RCV_SEL
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pmux_pingrp_config {
u32 pingrp:16; /* pin group PMUX_PINGRP_... */
u32 func:8; /* function to assign PMUX_FUNC_... */
u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
u32 tristate:2; /* tristate or normal PMUX_TRI_... */
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
u32 io:2; /* input or output PMUX_PIN_... */
u32 lock:2; /* lock enable/disable PMUX_PIN... */
u32 od:2; /* open-drain or push-pull driver */
u32 ioreset:2; /* input/output reset PMUX_PIN... */
#ifdef TEGRA_PMX_HAS_RCV_SEL
u32 rcv_sel:2; /* select between High and Normal */
/* VIL/VIH receivers */
#endif
#endif
};
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
/**
* Configure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
#ifdef TEGRA_PMX_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#define PMUX_SLWF_MAX 3
#define PMUX_SLWF_NONE -1
#define PMUX_SLWR_MIN 0
#define PMUX_SLWR_MAX 3
#define PMUX_SLWR_NONE -1
#define PMUX_DRVUP_MIN 0
#define PMUX_DRVUP_MAX 127
#define PMUX_DRVUP_NONE -1
#define PMUX_DRVDN_MIN 0
#define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
struct pmux_drvgrp_config {
u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
u32 slwf:3; /* falling edge slew */
u32 slwr:3; /* rising edge slew */
u32 drvup:8; /* pull-up drive strength */
u32 drvdn:8; /* pull-down drive strength */
u32 lpmd:3; /* low-power mode selection */
u32 schmt:2; /* schmidt enable */
u32 hsm:2; /* high-speed mode enable */
};
/**
* Set the GP pad configs
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len);
#endif /* TEGRA_PMX_HAS_DRVGRPS */
struct pmux_pingrp_desc {
u8 funcs[4];
#if defined(CONFIG_TEGRA20)
u8 ctl_id;
u8 pull_id;
#endif /* CONFIG_TEGRA20 */
};
extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
#endif /* _TEGRA_PINMUX_H_ */

223
arch/arm/include/asm/arch-tegra/usb.h
View file

@ -8,6 +8,189 @@
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[2];
#ifdef CONFIG_TEGRA20
/* 0x130 */
uint reserved4_2[4];
/* 0x140 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x150 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint async_tt_sts;
/* 0x160 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6; /* is this port_sc1 on some controllers? */
uint icusb_ctrl;
/* 0x170 */
uint ulpi_viewport;
uint reserved7;
uint endpt_nak;
uint endpt_nak_enable;
/* 0x180 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x1a0 */
uint reserved9;
uint otgsc;
uint usb_mode;
uint endpt_setup_stat;
/* 0x1b0 */
uint reserved10[20];
/* 0x200 */
uint reserved11[0x80];
#else
/* 0x130 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x140 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint reserved5_1;
/* 0x150 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6;
uint icusb_ctrl;
/* 0x160 */
uint ulpi_viewport;
uint reserved7[3];
/* 0x170 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x190 */
uint reserved9[8];
/* 0x1b0 */
uint reserved10;
uint hostpc1_devlc;
uint reserved10_1[2];
/* 0x1c0 */
uint reserved10_2[4];
/* 0x1d0 */
uint reserved10_3[4];
/* 0x1e0 */
uint reserved10_4[4];
/* 0x1f0 */
uint reserved10_5;
uint otgsc;
uint usb_mode;
uint reserved10_6;
/* 0x200 */
uint endpt_nak;
uint endpt_nak_enable;
uint endpt_setup_stat;
uint reserved11_1[0x7D];
#endif
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
#ifdef CONFIG_TEGRA20
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[4];
/* 0x424 */
uint ulpi_timing_ctrl_0;
uint ulpi_timing_ctrl_1;
uint reserved13[53];
#else
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[3];
/* 0x420 */
uint reserved13[56];
#endif
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE 1
@ -24,22 +207,46 @@
#define USB_PHY_CLK_VALID (1 << 7)
#define USB_SUSP_CLR (1 << 5)
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* USB2_IF_USB_SUSP_CTRL_0 */
#define ULPI_PHY_ENB (1 << 13)
/* USB2_IF_ULPI_TIMING_CTRL_0 */
#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
/* USB2_IF_ULPI_TIMING_CTRL_1 */
#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
#endif
/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/*
* Tegra 3 and later: Moved to Clock and Reset register space, see
* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
*/
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
#define UTMIP_PLLU_STABLE_COUNT_MASK \
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
/*
* Tegra 3 and later: Moved to Clock and Reset register space, see
* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
*/
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/* USBx_UTMIP_PLL_CFG1_0 */
/* Tegra 3 and later: Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
@ -91,11 +298,23 @@
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
/* PORTSC1, USB1, defined for Tegra20 */
#ifdef CONFIG_TEGRA20
/* PORTSC1, USB1 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
/* PORTSC, USB2, USB3 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
#define STS (1 << 29)
#else
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT 29
#define PTS_MASK (0x7U << PTS_SHIFT)
#define STS (1 << 28)
#endif
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2

836
arch/arm/include/asm/arch-tegra114/pinmux.h
View file

@ -1,616 +1,320 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA114_PINMUX_H_
#define _TEGRA114_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
* group which use this enum:
*
* - function
* - pullup / pulldown
* - tristate or normal
*/
enum pmux_pingrp {
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
PINGRP_ULPI_DATA1,
PINGRP_ULPI_DATA2,
PINGRP_ULPI_DATA3,
PINGRP_ULPI_DATA4,
PINGRP_ULPI_DATA5,
PINGRP_ULPI_DATA6,
PINGRP_ULPI_DATA7,
PINGRP_ULPI_CLK,
PINGRP_ULPI_DIR,
PINGRP_ULPI_NXT,
PINGRP_ULPI_STP,
PINGRP_DAP3_FS,
PINGRP_DAP3_DIN,
PINGRP_DAP3_DOUT,
PINGRP_DAP3_SCLK,
PINGRP_GPIO_PV0,
PINGRP_GPIO_PV1,
PINGRP_SDMMC1_CLK,
PINGRP_SDMMC1_CMD,
PINGRP_SDMMC1_DAT3,
PINGRP_SDMMC1_DAT2,
PINGRP_SDMMC1_DAT1,
PINGRP_SDMMC1_DAT0,
PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
PINGRP_CLK2_REQ,
PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
PINGRP_DDC_SCL,
PINGRP_DDC_SDA,
PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
PINGRP_UART2_TXD,
PINGRP_UART2_RTS_N,
PINGRP_UART2_CTS_N,
PINGRP_UART3_TXD,
PINGRP_UART3_RXD,
PINGRP_UART3_CTS_N,
PINGRP_UART3_RTS_N,
PINGRP_GPIO_PU0,
PINGRP_GPIO_PU1,
PINGRP_GPIO_PU2,
PINGRP_GPIO_PU3,
PINGRP_GPIO_PU4,
PINGRP_GPIO_PU5,
PINGRP_GPIO_PU6,
PINGRP_GEN1_I2C_SDA,
PINGRP_GEN1_I2C_SCL,
PINGRP_DAP4_FS,
PINGRP_DAP4_DIN,
PINGRP_DAP4_DOUT,
PINGRP_DAP4_SCLK,
PINGRP_CLK3_OUT,
PINGRP_CLK3_REQ,
PINGRP_GMI_WP_N,
PINGRP_GMI_IORDY,
PINGRP_GMI_WAIT,
PINGRP_GMI_ADV_N,
PINGRP_GMI_CLK,
PINGRP_GMI_CS0_N,
PINGRP_GMI_CS1_N,
PINGRP_GMI_CS2_N,
PINGRP_GMI_CS3_N,
PINGRP_GMI_CS4_N,
PINGRP_GMI_CS6_N,
PINGRP_GMI_CS7_N,
PINGRP_GMI_AD0,
PINGRP_GMI_AD1,
PINGRP_GMI_AD2,
PINGRP_GMI_AD3,
PINGRP_GMI_AD4,
PINGRP_GMI_AD5,
PINGRP_GMI_AD6,
PINGRP_GMI_AD7,
PINGRP_GMI_AD8,
PINGRP_GMI_AD9,
PINGRP_GMI_AD10,
PINGRP_GMI_AD11,
PINGRP_GMI_AD12,
PINGRP_GMI_AD13,
PINGRP_GMI_AD14,
PINGRP_GMI_AD15,
PINGRP_GMI_A16,
PINGRP_GMI_A17,
PINGRP_GMI_A18,
PINGRP_GMI_A19,
PINGRP_GMI_WR_N,
PINGRP_GMI_OE_N,
PINGRP_GMI_DQS,
PINGRP_GMI_RST_N,
PINGRP_GEN2_I2C_SCL,
PINGRP_GEN2_I2C_SDA,
PINGRP_SDMMC4_CLK,
PINGRP_SDMMC4_CMD,
PINGRP_SDMMC4_DAT0,
PINGRP_SDMMC4_DAT1,
PINGRP_SDMMC4_DAT2,
PINGRP_SDMMC4_DAT3,
PINGRP_SDMMC4_DAT4,
PINGRP_SDMMC4_DAT5,
PINGRP_SDMMC4_DAT6,
PINGRP_SDMMC4_DAT7,
PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
PINGRP_GPIO_PCC1,
PINGRP_GPIO_PBB0,
PINGRP_CAM_I2C_SCL,
PINGRP_CAM_I2C_SDA,
PINGRP_GPIO_PBB3,
PINGRP_GPIO_PBB4,
PINGRP_GPIO_PBB5,
PINGRP_GPIO_PBB6,
PINGRP_GPIO_PBB7,
PINGRP_GPIO_PCC2,
PINGRP_JTAG_RTCK,
PINGRP_PWR_I2C_SCL,
PINGRP_PWR_I2C_SDA,
PINGRP_KB_ROW0,
PINGRP_KB_ROW1,
PINGRP_KB_ROW2,
PINGRP_KB_ROW3,
PINGRP_KB_ROW4,
PINGRP_KB_ROW5,
PINGRP_KB_ROW6,
PINGRP_KB_ROW7,
PINGRP_KB_ROW8,
PINGRP_KB_ROW9,
PINGRP_KB_ROW10,
PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
PINGRP_KB_COL1,
PINGRP_KB_COL2,
PINGRP_KB_COL3,
PINGRP_KB_COL4,
PINGRP_KB_COL5,
PINGRP_KB_COL6,
PINGRP_KB_COL7,
PINGRP_CLK_32K_OUT,
PINGRP_SYS_CLK_REQ,
PINGRP_CORE_PWR_REQ,
PINGRP_CPU_PWR_REQ,
PINGRP_PWR_INT_N,
PINGRP_CLK_32K_IN,
PINGRP_OWR,
PINGRP_DAP1_FS,
PINGRP_DAP1_DIN,
PINGRP_DAP1_DOUT,
PINGRP_DAP1_SCLK,
PINGRP_CLK1_REQ,
PINGRP_CLK1_OUT,
PINGRP_SPDIF_IN,
PINGRP_SPDIF_OUT,
PINGRP_DAP2_FS,
PINGRP_DAP2_DIN,
PINGRP_DAP2_DOUT,
PINGRP_DAP2_SCLK,
PINGRP_DVFS_PWM,
PINGRP_GPIO_X1_AUD,
PINGRP_GPIO_X3_AUD,
PINGRP_DVFS_CLK,
PINGRP_GPIO_X4_AUD,
PINGRP_GPIO_X5_AUD,
PINGRP_GPIO_X6_AUD,
PINGRP_GPIO_X7_AUD,
PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
PINGRP_SDMMC3_CMD,
PINGRP_SDMMC3_DAT0,
PINGRP_SDMMC3_DAT1,
PINGRP_SDMMC3_DAT2,
PINGRP_SDMMC3_DAT3,
PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
PINGRP_SDMMC1_WP_N,
PINGRP_SDMMC3_CD_N,
PINGRP_GPIO_W2_AUD,
PINGRP_GPIO_W3_AUD,
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
PINGRP_USB_VBUS_EN1,
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
PINGRP_COUNT,
PMUX_PINGRP_ULPI_DATA0_PO1,
PMUX_PINGRP_ULPI_DATA1_PO2,
PMUX_PINGRP_ULPI_DATA2_PO3,
PMUX_PINGRP_ULPI_DATA3_PO4,
PMUX_PINGRP_ULPI_DATA4_PO5,
PMUX_PINGRP_ULPI_DATA5_PO6,
PMUX_PINGRP_ULPI_DATA6_PO7,
PMUX_PINGRP_ULPI_DATA7_PO0,
PMUX_PINGRP_ULPI_CLK_PY0,
PMUX_PINGRP_ULPI_DIR_PY1,
PMUX_PINGRP_ULPI_NXT_PY2,
PMUX_PINGRP_ULPI_STP_PY3,
PMUX_PINGRP_DAP3_FS_PP0,
PMUX_PINGRP_DAP3_DIN_PP1,
PMUX_PINGRP_DAP3_DOUT_PP2,
PMUX_PINGRP_DAP3_SCLK_PP3,
PMUX_PINGRP_PV0,
PMUX_PINGRP_PV1,
PMUX_PINGRP_SDMMC1_CLK_PZ0,
PMUX_PINGRP_SDMMC1_CMD_PZ1,
PMUX_PINGRP_SDMMC1_DAT3_PY4,
PMUX_PINGRP_SDMMC1_DAT2_PY5,
PMUX_PINGRP_SDMMC1_DAT1_PY6,
PMUX_PINGRP_SDMMC1_DAT0_PY7,
PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
PMUX_PINGRP_CLK2_REQ_PCC5,
PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
PMUX_PINGRP_DDC_SCL_PV4,
PMUX_PINGRP_DDC_SDA_PV5,
PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
PMUX_PINGRP_UART2_TXD_PC2,
PMUX_PINGRP_UART2_RTS_N_PJ6,
PMUX_PINGRP_UART2_CTS_N_PJ5,
PMUX_PINGRP_UART3_TXD_PW6,
PMUX_PINGRP_UART3_RXD_PW7,
PMUX_PINGRP_UART3_CTS_N_PA1,
PMUX_PINGRP_UART3_RTS_N_PC0,
PMUX_PINGRP_PU0,
PMUX_PINGRP_PU1,
PMUX_PINGRP_PU2,
PMUX_PINGRP_PU3,
PMUX_PINGRP_PU4,
PMUX_PINGRP_PU5,
PMUX_PINGRP_PU6,
PMUX_PINGRP_GEN1_I2C_SDA_PC5,
PMUX_PINGRP_GEN1_I2C_SCL_PC4,
PMUX_PINGRP_DAP4_FS_PP4,
PMUX_PINGRP_DAP4_DIN_PP5,
PMUX_PINGRP_DAP4_DOUT_PP6,
PMUX_PINGRP_DAP4_SCLK_PP7,
PMUX_PINGRP_CLK3_OUT_PEE0,
PMUX_PINGRP_CLK3_REQ_PEE1,
PMUX_PINGRP_GMI_WP_N_PC7,
PMUX_PINGRP_GMI_IORDY_PI5,
PMUX_PINGRP_GMI_WAIT_PI7,
PMUX_PINGRP_GMI_ADV_N_PK0,
PMUX_PINGRP_GMI_CLK_PK1,
PMUX_PINGRP_GMI_CS0_N_PJ0,
PMUX_PINGRP_GMI_CS1_N_PJ2,
PMUX_PINGRP_GMI_CS2_N_PK3,
PMUX_PINGRP_GMI_CS3_N_PK4,
PMUX_PINGRP_GMI_CS4_N_PK2,
PMUX_PINGRP_GMI_CS6_N_PI3,
PMUX_PINGRP_GMI_CS7_N_PI6,
PMUX_PINGRP_GMI_AD0_PG0,
PMUX_PINGRP_GMI_AD1_PG1,
PMUX_PINGRP_GMI_AD2_PG2,
PMUX_PINGRP_GMI_AD3_PG3,
PMUX_PINGRP_GMI_AD4_PG4,
PMUX_PINGRP_GMI_AD5_PG5,
PMUX_PINGRP_GMI_AD6_PG6,
PMUX_PINGRP_GMI_AD7_PG7,
PMUX_PINGRP_GMI_AD8_PH0,
PMUX_PINGRP_GMI_AD9_PH1,
PMUX_PINGRP_GMI_AD10_PH2,
PMUX_PINGRP_GMI_AD11_PH3,
PMUX_PINGRP_GMI_AD12_PH4,
PMUX_PINGRP_GMI_AD13_PH5,
PMUX_PINGRP_GMI_AD14_PH6,
PMUX_PINGRP_GMI_AD15_PH7,
PMUX_PINGRP_GMI_A16_PJ7,
PMUX_PINGRP_GMI_A17_PB0,
PMUX_PINGRP_GMI_A18_PB1,
PMUX_PINGRP_GMI_A19_PK7,
PMUX_PINGRP_GMI_WR_N_PI0,
PMUX_PINGRP_GMI_OE_N_PI1,
PMUX_PINGRP_GMI_DQS_P_PJ3,
PMUX_PINGRP_GMI_RST_N_PI4,
PMUX_PINGRP_GEN2_I2C_SCL_PT5,
PMUX_PINGRP_GEN2_I2C_SDA_PT6,
PMUX_PINGRP_SDMMC4_CLK_PCC4,
PMUX_PINGRP_SDMMC4_CMD_PT7,
PMUX_PINGRP_SDMMC4_DAT0_PAA0,
PMUX_PINGRP_SDMMC4_DAT1_PAA1,
PMUX_PINGRP_SDMMC4_DAT2_PAA2,
PMUX_PINGRP_SDMMC4_DAT3_PAA3,
PMUX_PINGRP_SDMMC4_DAT4_PAA4,
PMUX_PINGRP_SDMMC4_DAT5_PAA5,
PMUX_PINGRP_SDMMC4_DAT6_PAA6,
PMUX_PINGRP_SDMMC4_DAT7_PAA7,
PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
PMUX_PINGRP_PCC1,
PMUX_PINGRP_PBB0,
PMUX_PINGRP_CAM_I2C_SCL_PBB1,
PMUX_PINGRP_CAM_I2C_SDA_PBB2,
PMUX_PINGRP_PBB3,
PMUX_PINGRP_PBB4,
PMUX_PINGRP_PBB5,
PMUX_PINGRP_PBB6,
PMUX_PINGRP_PBB7,
PMUX_PINGRP_PCC2,
PMUX_PINGRP_JTAG_RTCK,
PMUX_PINGRP_PWR_I2C_SCL_PZ6,
PMUX_PINGRP_PWR_I2C_SDA_PZ7,
PMUX_PINGRP_KB_ROW0_PR0,
PMUX_PINGRP_KB_ROW1_PR1,
PMUX_PINGRP_KB_ROW2_PR2,
PMUX_PINGRP_KB_ROW3_PR3,
PMUX_PINGRP_KB_ROW4_PR4,
PMUX_PINGRP_KB_ROW5_PR5,
PMUX_PINGRP_KB_ROW6_PR6,
PMUX_PINGRP_KB_ROW7_PR7,
PMUX_PINGRP_KB_ROW8_PS0,
PMUX_PINGRP_KB_ROW9_PS1,
PMUX_PINGRP_KB_ROW10_PS2,
PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
PMUX_PINGRP_KB_COL1_PQ1,
PMUX_PINGRP_KB_COL2_PQ2,
PMUX_PINGRP_KB_COL3_PQ3,
PMUX_PINGRP_KB_COL4_PQ4,
PMUX_PINGRP_KB_COL5_PQ5,
PMUX_PINGRP_KB_COL6_PQ6,
PMUX_PINGRP_KB_COL7_PQ7,
PMUX_PINGRP_CLK_32K_OUT_PA0,
PMUX_PINGRP_SYS_CLK_REQ_PZ5,
PMUX_PINGRP_CORE_PWR_REQ,
PMUX_PINGRP_CPU_PWR_REQ,
PMUX_PINGRP_PWR_INT_N,
PMUX_PINGRP_CLK_32K_IN,
PMUX_PINGRP_OWR,
PMUX_PINGRP_DAP1_FS_PN0,
PMUX_PINGRP_DAP1_DIN_PN1,
PMUX_PINGRP_DAP1_DOUT_PN2,
PMUX_PINGRP_DAP1_SCLK_PN3,
PMUX_PINGRP_CLK1_REQ_PEE2,
PMUX_PINGRP_CLK1_OUT_PW4,
PMUX_PINGRP_SPDIF_IN_PK6,
PMUX_PINGRP_SPDIF_OUT_PK5,
PMUX_PINGRP_DAP2_FS_PA2,
PMUX_PINGRP_DAP2_DIN_PA4,
PMUX_PINGRP_DAP2_DOUT_PA5,
PMUX_PINGRP_DAP2_SCLK_PA3,
PMUX_PINGRP_DVFS_PWM_PX0,
PMUX_PINGRP_GPIO_X1_AUD_PX1,
PMUX_PINGRP_GPIO_X3_AUD_PX3,
PMUX_PINGRP_DVFS_CLK_PX2,
PMUX_PINGRP_GPIO_X4_AUD_PX4,
PMUX_PINGRP_GPIO_X5_AUD_PX5,
PMUX_PINGRP_GPIO_X6_AUD_PX6,
PMUX_PINGRP_GPIO_X7_AUD_PX7,
PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
PMUX_PINGRP_SDMMC3_CMD_PA7,
PMUX_PINGRP_SDMMC3_DAT0_PB7,
PMUX_PINGRP_SDMMC3_DAT1_PB6,
PMUX_PINGRP_SDMMC3_DAT2_PB5,
PMUX_PINGRP_SDMMC3_DAT3_PB4,
PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
PMUX_PINGRP_SDMMC1_WP_N_PV3,
PMUX_PINGRP_SDMMC3_CD_N_PV2,
PMUX_PINGRP_GPIO_W2_AUD_PW2,
PMUX_PINGRP_GPIO_W3_AUD_PW3,
PMUX_PINGRP_USB_VBUS_EN0_PN4,
PMUX_PINGRP_USB_VBUS_EN1_PN5,
PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
PMUX_PINGRP_GMI_CLK_LB,
PMUX_PINGRP_RESET_OUT_N,
PMUX_PINGRP_COUNT,
};
enum pdrive_pingrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
PDRIVE_PINGROUP_AT2,
PDRIVE_PINGROUP_AT3,
PDRIVE_PINGROUP_AT4,
PDRIVE_PINGROUP_AT5,
PDRIVE_PINGROUP_CDEV1,
PDRIVE_PINGROUP_CDEV2,
PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
PDRIVE_PINGROUP_DAP2,
PDRIVE_PINGROUP_DAP3,
PDRIVE_PINGROUP_DAP4,
PDRIVE_PINGROUP_DBG,
PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
PDRIVE_PINGROUP_SPI,
PDRIVE_PINGROUP_UAA,
PDRIVE_PINGROUP_UAB,
PDRIVE_PINGROUP_UART2,
PDRIVE_PINGROUP_UART3,
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
PDRIVE_PINGROUP_GMA,
PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
PDRIVE_PINGROUP_GMF,
PDRIVE_PINGROUP_GMG,
PDRIVE_PINGROUP_GMH,
PDRIVE_PINGROUP_OWR,
PDRIVE_PINGROUP_UAD,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
PDRIVE_PINGROUP_DAP5,
PDRIVE_PINGROUP_VBUS,
PDRIVE_PINGROUP_AO3,
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
enum pmux_drvgrp {
PMUX_DRVGRP_AO1,
PMUX_DRVGRP_AO2,
PMUX_DRVGRP_AT1,
PMUX_DRVGRP_AT2,
PMUX_DRVGRP_AT3,
PMUX_DRVGRP_AT4,
PMUX_DRVGRP_AT5,
PMUX_DRVGRP_CDEV1,
PMUX_DRVGRP_CDEV2,
PMUX_DRVGRP_DAP1 = (0x28 / 4),
PMUX_DRVGRP_DAP2,
PMUX_DRVGRP_DAP3,
PMUX_DRVGRP_DAP4,
PMUX_DRVGRP_DBG,
PMUX_DRVGRP_SDIO3 = (0x48 / 4),
PMUX_DRVGRP_SPI,
PMUX_DRVGRP_UAA,
PMUX_DRVGRP_UAB,
PMUX_DRVGRP_UART2,
PMUX_DRVGRP_UART3,
PMUX_DRVGRP_SDIO1 = (0x84 / 4),
PMUX_DRVGRP_DDC = (0x94 / 4),
PMUX_DRVGRP_GMA,
PMUX_DRVGRP_GME = (0xa8 / 4),
PMUX_DRVGRP_GMF,
PMUX_DRVGRP_GMG,
PMUX_DRVGRP_GMH,
PMUX_DRVGRP_OWR,
PMUX_DRVGRP_UDA,
PMUX_DRVGRP_DEV3 = (0xc4 / 4),
PMUX_DRVGRP_CEC = (0xd0 / 4),
PMUX_DRVGRP_AT6 = (0x12c / 4),
PMUX_DRVGRP_DAP5,
PMUX_DRVGRP_USB_VBUS_EN,
PMUX_DRVGRP_AO3,
PMUX_DRVGRP_HV0,
PMUX_DRVGRP_SDIO4,
PMUX_DRVGRP_AO0,
PMUX_DRVGRP_COUNT,
};
/*
* Functions which can be assigned to each of the pin groups. The values here
* bear no relation to the values programmed into pinmux registers and are
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,
PMUX_FUNC_CRT,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DAP3,
PMUX_FUNC_DAP4,
PMUX_FUNC_DAP5,
PMUX_FUNC_DISPA,
PMUX_FUNC_DISPB,
PMUX_FUNC_EMC_TEST0_DLL,
PMUX_FUNC_EMC_TEST1_DLL,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_INT,
PMUX_FUNC_HDMI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_IDE,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
PMUX_FUNC_OSC,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
PMUX_FUNC_PLLA_OUT,
PMUX_FUNC_PLLC_OUT1,
PMUX_FUNC_PLLM_OUT1,
PMUX_FUNC_PLLP_OUT2,
PMUX_FUNC_PLLP_OUT3,
PMUX_FUNC_PLLP_OUT4,
PMUX_FUNC_PWM,
PMUX_FUNC_PWR_INTR,
PMUX_FUNC_PWR_ON,
PMUX_FUNC_RTCK,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_TRACE,
PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
/* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
PMUX_FUNC_DAPSDMMC2,
PMUX_FUNC_DDR,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
PMUX_FUNC_DISPLAYA,
PMUX_FUNC_DISPLAYA_ALT,
PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DTV,
PMUX_FUNC_VI_ALT1,
PMUX_FUNC_VI_ALT2,
PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
PMUX_FUNC_IRDA,
PMUX_FUNC_KBC,
PMUX_FUNC_NAND,
PMUX_FUNC_NAND_ALT,
PMUX_FUNC_POPSDIO4,
PMUX_FUNC_POPSDMMC4,
PMUX_FUNC_OWR,
PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
PMUX_FUNC_SATA,
PMUX_FUNC_PWRON,
PMUX_FUNC_RESET_OUT_N,
PMUX_FUNC_RTCK,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
PMUX_FUNC_SOC,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
PMUX_FUNC_TRACE,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_ULPI,
PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
/* End of Tegra3 MUX selectors */
PMUX_FUNC_USB,
PMUX_FUNC_SOC,
PMUX_FUNC_CPU,
PMUX_FUNC_CLK,
PMUX_FUNC_PWRON,
PMUX_FUNC_PMI,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
PMUX_FUNC_RSVD4 = 0x8003,
PMUX_FUNC_VI,
PMUX_FUNC_VI_ALT1,
PMUX_FUNC_VI_ALT3,
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
PMUX_FUNC_COUNT,
};
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
/* return 1 if a pingrp is in range */
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* return 1 if a pin_pupd_is in range */
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
((pupd) <= PMUX_PULL_UP))
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
/* return 1 if a pin_tristate_is in range */
#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
&& ((tristate) <= PMUX_TRI_TRISTATE))
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
((io) <= PMUX_PIN_INPUT))
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
((lock) <= PMUX_PIN_LOCK_ENABLE))
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
((od) <= PMUX_PIN_OD_ENABLE))
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
#define PGRP_SLWR_MAX PGRP_SLWF_MAX
#define PGRP_DRVUP_NONE -1
#define PGRP_DRVUP_MAX 127
#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
#define PGRP_SCHMT_NONE -1
#define PGRP_HSM_NONE PGRP_SCHMT_NONE
/* return 1 if a padgrp is in range */
#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
/* return 1 if a slew-rate rising/falling edge value is in range */
#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
/* return 1 if a driver output pull-up/down strength code value is in range */
#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
/* return 1 if a low-power mode value is in range */
#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
/* Defines a pin group cfg's low-power mode select */
enum pgrp_lpmd {
PGRP_LPMD_X8 = 0,
PGRP_LPMD_X4,
PGRP_LPMD_X2,
PGRP_LPMD_X,
PGRP_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pgrp_schmt {
PGRP_SCHMT_DISABLE = 0,
PGRP_SCHMT_ENABLE = 1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pgrp_hsm {
PGRP_HSM_DISABLE = 0,
PGRP_HSM_ENABLE = 1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
struct padctrl_config {
enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
int slwf; /* falling edge slew */
int slwr; /* rising edge slew */
int drvup; /* pull-up drive strength */
int drvdn; /* pull-down drive strength */
enum pgrp_lpmd lpmd; /* low-power mode selection */
enum pgrp_schmt schmt; /* schmidt enable */
enum pgrp_hsm hsm; /* high-speed mode enable */
};
/* t114 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
PDRIVE_PINGROUP_COUNT)
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
uint pmt_reserved5[PMUX_OFFSET];
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
};
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pingroup_config {
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
enum pmux_func func; /* function to assign FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
/* VIL/VIH receivers */
};
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the complete configuration for a pin group */
void pinmux_config_pingroup(struct pingroup_config *config);
/* Set a pin group to tristate or normal */
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
/**
* Configure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
/**
* Set the GP pad configs
*
* @param config List of config items
* @param len Number of config items in list
*/
void padgrp_config_table(struct padctrl_config *config, int len);
#endif /* _TEGRA114_PINMUX_H_ */
#endif /* _TEGRA114_PINMUX_H_ */

156
arch/arm/include/asm/arch-tegra114/usb.h
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@ -1,156 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2013 NVIDIA Corporation
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA114_USB_H_
#define _TEGRA114_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[2];
/* 0x130 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x140 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint reserved5_1;
/* 0x150 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6;
uint icusb_ctrl;
/* 0x160 */
uint ulpi_viewport;
uint reserved7[3];
/* 0x170 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x190 */
uint reserved9[8];
/* 0x1b0 */
uint reserved10;
uint hostpc1_devlc;
uint reserved10_1[2];
/* 0x1c0 */
uint reserved10_2[4];
/* 0x1d0 */
uint reserved10_3[4];
/* 0x1e0 */
uint reserved10_4[4];
/* 0x1f0 */
uint reserved10_5;
uint otgsc;
uint usb_mode;
uint reserved10_6;
/* 0x200 */
uint endpt_nak;
uint endpt_nak_enable;
uint endpt_setup_stat;
uint reserved11_1[0x7D];
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[3];
/* 0x420 */
uint reserved13[56];
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT 29
#define PTS_MASK (0x7U << PTS_SHIFT)
#define STS (1 << 28)
#endif /* _TEGRA114_USB_H_ */

870
arch/arm/include/asm/arch-tegra124/pinmux.h
View file

@ -1,620 +1,342 @@
/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_PINMUX_H_
#define _TEGRA124_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
* group which use this enum:
*
* - function
* - pullup / pulldown
* - tristate or normal
*/
enum pmux_pingrp {
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
PINGRP_ULPI_DATA1,
PINGRP_ULPI_DATA2,
PINGRP_ULPI_DATA3,
PINGRP_ULPI_DATA4,
PINGRP_ULPI_DATA5,
PINGRP_ULPI_DATA6,
PINGRP_ULPI_DATA7,
PINGRP_ULPI_CLK,
PINGRP_ULPI_DIR,
PINGRP_ULPI_NXT,
PINGRP_ULPI_STP,
PINGRP_DAP3_FS,
PINGRP_DAP3_DIN,
PINGRP_DAP3_DOUT,
PINGRP_DAP3_SCLK,
PINGRP_GPIO_PV0,
PINGRP_GPIO_PV1,
PINGRP_SDMMC1_CLK,
PINGRP_SDMMC1_CMD,
PINGRP_SDMMC1_DAT3,
PINGRP_SDMMC1_DAT2,
PINGRP_SDMMC1_DAT1,
PINGRP_SDMMC1_DAT0,
PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
PINGRP_CLK2_REQ,
PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
PINGRP_DDC_SCL,
PINGRP_DDC_SDA,
PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
PINGRP_UART2_TXD,
PINGRP_UART2_RTS_N,
PINGRP_UART2_CTS_N,
PINGRP_UART3_TXD,
PINGRP_UART3_RXD,
PINGRP_UART3_CTS_N,
PINGRP_UART3_RTS_N,
PINGRP_GPIO_PU0,
PINGRP_GPIO_PU1,
PINGRP_GPIO_PU2,
PINGRP_GPIO_PU3,
PINGRP_GPIO_PU4,
PINGRP_GPIO_PU5,
PINGRP_GPIO_PU6,
PINGRP_GEN1_I2C_SDA,
PINGRP_GEN1_I2C_SCL,
PINGRP_DAP4_FS,
PINGRP_DAP4_DIN,
PINGRP_DAP4_DOUT,
PINGRP_DAP4_SCLK,
PINGRP_CLK3_OUT,
PINGRP_CLK3_REQ,
/* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
PINGRP_GPIO_PC7, /* offset 0x31c0 */
PINGRP_GPIO_PI5,
PINGRP_GPIO_PI7,
PINGRP_GPIO_PK0,
PINGRP_GPIO_PK1,
PINGRP_GPIO_PJ0,
PINGRP_GPIO_PJ2,
PINGRP_GPIO_PK3,
PINGRP_GPIO_PK4,
PINGRP_GPIO_PK2,
PINGRP_GPIO_PI3,
PINGRP_GPIO_PI6,
PINGRP_GPIO_PG0,
PINGRP_GPIO_PG1,
PINGRP_GPIO_PG2,
PINGRP_GPIO_PG3,
PINGRP_GPIO_PG4,
PINGRP_GPIO_PG5,
PINGRP_GPIO_PG6,
PINGRP_GPIO_PG7,
PINGRP_GPIO_PH0,
PINGRP_GPIO_PH1,
PINGRP_GPIO_PH2,
PINGRP_GPIO_PH3,
PINGRP_GPIO_PH4,
PINGRP_GPIO_PH5,
PINGRP_GPIO_PH6,
PINGRP_GPIO_PH7,
PINGRP_GPIO_PJ7,
PINGRP_GPIO_PB0,
PINGRP_GPIO_PB1,
PINGRP_GPIO_PK7,
PINGRP_GPIO_PI0,
PINGRP_GPIO_PI1,
PINGRP_GPIO_PI2,
PINGRP_GPIO_PI4, /* offset 0x324c */
PINGRP_GEN2_I2C_SCL,
PINGRP_GEN2_I2C_SDA,
PINGRP_SDMMC4_CLK,
PINGRP_SDMMC4_CMD,
PINGRP_SDMMC4_DAT0,
PINGRP_SDMMC4_DAT1,
PINGRP_SDMMC4_DAT2,
PINGRP_SDMMC4_DAT3,
PINGRP_SDMMC4_DAT4,
PINGRP_SDMMC4_DAT5,
PINGRP_SDMMC4_DAT6,
PINGRP_SDMMC4_DAT7,
PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
PINGRP_GPIO_PCC1,
PINGRP_GPIO_PBB0,
PINGRP_CAM_I2C_SCL,
PINGRP_CAM_I2C_SDA,
PINGRP_GPIO_PBB3,
PINGRP_GPIO_PBB4,
PINGRP_GPIO_PBB5,
PINGRP_GPIO_PBB6,
PINGRP_GPIO_PBB7,
PINGRP_GPIO_PCC2,
PINGRP_JTAG_RTCK,
PINGRP_PWR_I2C_SCL,
PINGRP_PWR_I2C_SDA,
PINGRP_KB_ROW0,
PINGRP_KB_ROW1,
PINGRP_KB_ROW2,
PINGRP_KB_ROW3,
PINGRP_KB_ROW4,
PINGRP_KB_ROW5,
PINGRP_KB_ROW6,
PINGRP_KB_ROW7,
PINGRP_KB_ROW8,
PINGRP_KB_ROW9,
PINGRP_KB_ROW10,
PINGRP_KB_ROW11,
PINGRP_KB_ROW12,
PINGRP_KB_ROW13,
PINGRP_KB_ROW14,
PINGRP_KB_ROW15,
PINGRP_KB_COL0, /* offset 0x32fc */
PINGRP_KB_COL1,
PINGRP_KB_COL2,
PINGRP_KB_COL3,
PINGRP_KB_COL4,
PINGRP_KB_COL5,
PINGRP_KB_COL6,
PINGRP_KB_COL7,
PINGRP_CLK_32K_OUT,
PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
PINGRP_CPU_PWR_REQ,
PINGRP_PWR_INT_N,
PINGRP_CLK_32K_IN,
PINGRP_OWR,
PINGRP_DAP1_FS,
PINGRP_DAP1_DIN,
PINGRP_DAP1_DOUT,
PINGRP_DAP1_SCLK,
PINGRP_CLK1_REQ,
PINGRP_CLK1_OUT,
PINGRP_SPDIF_IN,
PINGRP_SPDIF_OUT,
PINGRP_DAP2_FS,
PINGRP_DAP2_DIN,
PINGRP_DAP2_DOUT,
PINGRP_DAP2_SCLK,
PINGRP_DVFS_PWM,
PINGRP_GPIO_X1_AUD,
PINGRP_GPIO_X3_AUD,
PINGRP_DVFS_CLK,
PINGRP_GPIO_X4_AUD,
PINGRP_GPIO_X5_AUD,
PINGRP_GPIO_X6_AUD,
PINGRP_GPIO_X7_AUD,
PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
PINGRP_SDMMC3_CMD,
PINGRP_SDMMC3_DAT0,
PINGRP_SDMMC3_DAT1,
PINGRP_SDMMC3_DAT2,
PINGRP_SDMMC3_DAT3,
PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
PINGRP_PEX_L0_CLKREQ,
PINGRP_PEX_WAKE,
PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
PINGRP_PEX_L1_CLKREQ,
PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
PINGRP_SDMMC1_WP_N,
PINGRP_SDMMC3_CD_N,
PINGRP_GPIO_W2_AUD,
PINGRP_GPIO_W3_AUD,
PINGRP_USB_VBUS_EN0,
PINGRP_USB_VBUS_EN1,
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
PINGRP_GMI_CLK_LB,
PINGRP_RESET_OUT_N,
PINGRP_KB_ROW16, /* offset 0x340c */
PINGRP_KB_ROW17,
PINGRP_USB_VBUS_EN2,
PINGRP_GPIO_PFF2,
PINGRP_DP_HPD, /* last reg offset = 0x3430 */
PINGRP_COUNT,
PMUX_PINGRP_ULPI_DATA0_PO1,
PMUX_PINGRP_ULPI_DATA1_PO2,
PMUX_PINGRP_ULPI_DATA2_PO3,
PMUX_PINGRP_ULPI_DATA3_PO4,
PMUX_PINGRP_ULPI_DATA4_PO5,
PMUX_PINGRP_ULPI_DATA5_PO6,
PMUX_PINGRP_ULPI_DATA6_PO7,
PMUX_PINGRP_ULPI_DATA7_PO0,
PMUX_PINGRP_ULPI_CLK_PY0,
PMUX_PINGRP_ULPI_DIR_PY1,
PMUX_PINGRP_ULPI_NXT_PY2,
PMUX_PINGRP_ULPI_STP_PY3,
PMUX_PINGRP_DAP3_FS_PP0,
PMUX_PINGRP_DAP3_DIN_PP1,
PMUX_PINGRP_DAP3_DOUT_PP2,
PMUX_PINGRP_DAP3_SCLK_PP3,
PMUX_PINGRP_PV0,
PMUX_PINGRP_PV1,
PMUX_PINGRP_SDMMC1_CLK_PZ0,
PMUX_PINGRP_SDMMC1_CMD_PZ1,
PMUX_PINGRP_SDMMC1_DAT3_PY4,
PMUX_PINGRP_SDMMC1_DAT2_PY5,
PMUX_PINGRP_SDMMC1_DAT1_PY6,
PMUX_PINGRP_SDMMC1_DAT0_PY7,
PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
PMUX_PINGRP_CLK2_REQ_PCC5,
PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
PMUX_PINGRP_DDC_SCL_PV4,
PMUX_PINGRP_DDC_SDA_PV5,
PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
PMUX_PINGRP_UART2_TXD_PC2,
PMUX_PINGRP_UART2_RTS_N_PJ6,
PMUX_PINGRP_UART2_CTS_N_PJ5,
PMUX_PINGRP_UART3_TXD_PW6,
PMUX_PINGRP_UART3_RXD_PW7,
PMUX_PINGRP_UART3_CTS_N_PA1,
PMUX_PINGRP_UART3_RTS_N_PC0,
PMUX_PINGRP_PU0,
PMUX_PINGRP_PU1,
PMUX_PINGRP_PU2,
PMUX_PINGRP_PU3,
PMUX_PINGRP_PU4,
PMUX_PINGRP_PU5,
PMUX_PINGRP_PU6,
PMUX_PINGRP_GEN1_I2C_SDA_PC5,
PMUX_PINGRP_GEN1_I2C_SCL_PC4,
PMUX_PINGRP_DAP4_FS_PP4,
PMUX_PINGRP_DAP4_DIN_PP5,
PMUX_PINGRP_DAP4_DOUT_PP6,
PMUX_PINGRP_DAP4_SCLK_PP7,
PMUX_PINGRP_CLK3_OUT_PEE0,
PMUX_PINGRP_CLK3_REQ_PEE1,
PMUX_PINGRP_PC7,
PMUX_PINGRP_PI5,
PMUX_PINGRP_PI7,
PMUX_PINGRP_PK0,
PMUX_PINGRP_PK1,
PMUX_PINGRP_PJ0,
PMUX_PINGRP_PJ2,
PMUX_PINGRP_PK3,
PMUX_PINGRP_PK4,
PMUX_PINGRP_PK2,
PMUX_PINGRP_PI3,
PMUX_PINGRP_PI6,
PMUX_PINGRP_PG0,
PMUX_PINGRP_PG1,
PMUX_PINGRP_PG2,
PMUX_PINGRP_PG3,
PMUX_PINGRP_PG4,
PMUX_PINGRP_PG5,
PMUX_PINGRP_PG6,
PMUX_PINGRP_PG7,
PMUX_PINGRP_PH0,
PMUX_PINGRP_PH1,
PMUX_PINGRP_PH2,
PMUX_PINGRP_PH3,
PMUX_PINGRP_PH4,
PMUX_PINGRP_PH5,
PMUX_PINGRP_PH6,
PMUX_PINGRP_PH7,
PMUX_PINGRP_PJ7,
PMUX_PINGRP_PB0,
PMUX_PINGRP_PB1,
PMUX_PINGRP_PK7,
PMUX_PINGRP_PI0,
PMUX_PINGRP_PI1,
PMUX_PINGRP_PI2,
PMUX_PINGRP_PI4,
PMUX_PINGRP_GEN2_I2C_SCL_PT5,
PMUX_PINGRP_GEN2_I2C_SDA_PT6,
PMUX_PINGRP_SDMMC4_CLK_PCC4,
PMUX_PINGRP_SDMMC4_CMD_PT7,
PMUX_PINGRP_SDMMC4_DAT0_PAA0,
PMUX_PINGRP_SDMMC4_DAT1_PAA1,
PMUX_PINGRP_SDMMC4_DAT2_PAA2,
PMUX_PINGRP_SDMMC4_DAT3_PAA3,
PMUX_PINGRP_SDMMC4_DAT4_PAA4,
PMUX_PINGRP_SDMMC4_DAT5_PAA5,
PMUX_PINGRP_SDMMC4_DAT6_PAA6,
PMUX_PINGRP_SDMMC4_DAT7_PAA7,
PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
PMUX_PINGRP_PCC1,
PMUX_PINGRP_PBB0,
PMUX_PINGRP_CAM_I2C_SCL_PBB1,
PMUX_PINGRP_CAM_I2C_SDA_PBB2,
PMUX_PINGRP_PBB3,
PMUX_PINGRP_PBB4,
PMUX_PINGRP_PBB5,
PMUX_PINGRP_PBB6,
PMUX_PINGRP_PBB7,
PMUX_PINGRP_PCC2,
PMUX_PINGRP_JTAG_RTCK,
PMUX_PINGRP_PWR_I2C_SCL_PZ6,
PMUX_PINGRP_PWR_I2C_SDA_PZ7,
PMUX_PINGRP_KB_ROW0_PR0,
PMUX_PINGRP_KB_ROW1_PR1,
PMUX_PINGRP_KB_ROW2_PR2,
PMUX_PINGRP_KB_ROW3_PR3,
PMUX_PINGRP_KB_ROW4_PR4,
PMUX_PINGRP_KB_ROW5_PR5,
PMUX_PINGRP_KB_ROW6_PR6,
PMUX_PINGRP_KB_ROW7_PR7,
PMUX_PINGRP_KB_ROW8_PS0,
PMUX_PINGRP_KB_ROW9_PS1,
PMUX_PINGRP_KB_ROW10_PS2,
PMUX_PINGRP_KB_ROW11_PS3,
PMUX_PINGRP_KB_ROW12_PS4,
PMUX_PINGRP_KB_ROW13_PS5,
PMUX_PINGRP_KB_ROW14_PS6,
PMUX_PINGRP_KB_ROW15_PS7,
PMUX_PINGRP_KB_COL0_PQ0,
PMUX_PINGRP_KB_COL1_PQ1,
PMUX_PINGRP_KB_COL2_PQ2,
PMUX_PINGRP_KB_COL3_PQ3,
PMUX_PINGRP_KB_COL4_PQ4,
PMUX_PINGRP_KB_COL5_PQ5,
PMUX_PINGRP_KB_COL6_PQ6,
PMUX_PINGRP_KB_COL7_PQ7,
PMUX_PINGRP_CLK_32K_OUT_PA0,
PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
PMUX_PINGRP_CPU_PWR_REQ,
PMUX_PINGRP_PWR_INT_N,
PMUX_PINGRP_CLK_32K_IN,
PMUX_PINGRP_OWR,
PMUX_PINGRP_DAP1_FS_PN0,
PMUX_PINGRP_DAP1_DIN_PN1,
PMUX_PINGRP_DAP1_DOUT_PN2,
PMUX_PINGRP_DAP1_SCLK_PN3,
PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
PMUX_PINGRP_DAP_MCLK1_PW4,
PMUX_PINGRP_SPDIF_IN_PK6,
PMUX_PINGRP_SPDIF_OUT_PK5,
PMUX_PINGRP_DAP2_FS_PA2,
PMUX_PINGRP_DAP2_DIN_PA4,
PMUX_PINGRP_DAP2_DOUT_PA5,
PMUX_PINGRP_DAP2_SCLK_PA3,
PMUX_PINGRP_DVFS_PWM_PX0,
PMUX_PINGRP_GPIO_X1_AUD_PX1,
PMUX_PINGRP_GPIO_X3_AUD_PX3,
PMUX_PINGRP_DVFS_CLK_PX2,
PMUX_PINGRP_GPIO_X4_AUD_PX4,
PMUX_PINGRP_GPIO_X5_AUD_PX5,
PMUX_PINGRP_GPIO_X6_AUD_PX6,
PMUX_PINGRP_GPIO_X7_AUD_PX7,
PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
PMUX_PINGRP_SDMMC3_CMD_PA7,
PMUX_PINGRP_SDMMC3_DAT0_PB7,
PMUX_PINGRP_SDMMC3_DAT1_PB6,
PMUX_PINGRP_SDMMC3_DAT2_PB5,
PMUX_PINGRP_SDMMC3_DAT3_PB4,
PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
PMUX_PINGRP_PEX_WAKE_N_PDD3,
PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
PMUX_PINGRP_SDMMC1_WP_N_PV3,
PMUX_PINGRP_SDMMC3_CD_N_PV2,
PMUX_PINGRP_GPIO_W2_AUD_PW2,
PMUX_PINGRP_GPIO_W3_AUD_PW3,
PMUX_PINGRP_USB_VBUS_EN0_PN4,
PMUX_PINGRP_USB_VBUS_EN1_PN5,
PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
PMUX_PINGRP_GMI_CLK_LB,
PMUX_PINGRP_RESET_OUT_N,
PMUX_PINGRP_KB_ROW16_PT0,
PMUX_PINGRP_KB_ROW17_PT1,
PMUX_PINGRP_USB_VBUS_EN2_PFF1,
PMUX_PINGRP_PFF2,
PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
PMUX_PINGRP_COUNT,
};
enum pdrive_pingrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
PDRIVE_PINGROUP_AT2,
PDRIVE_PINGROUP_AT3,
PDRIVE_PINGROUP_AT4,
PDRIVE_PINGROUP_AT5,
PDRIVE_PINGROUP_CDEV1,
PDRIVE_PINGROUP_CDEV2,
PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
PDRIVE_PINGROUP_DAP2,
PDRIVE_PINGROUP_DAP3,
PDRIVE_PINGROUP_DAP4,
PDRIVE_PINGROUP_DBG,
PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
PDRIVE_PINGROUP_SPI,
PDRIVE_PINGROUP_UAA,
PDRIVE_PINGROUP_UAB,
PDRIVE_PINGROUP_UART2,
PDRIVE_PINGROUP_UART3,
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
PDRIVE_PINGROUP_GMA,
PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
PDRIVE_PINGROUP_GMF,
PDRIVE_PINGROUP_GMG,
PDRIVE_PINGROUP_GMH,
PDRIVE_PINGROUP_OWR,
PDRIVE_PINGROUP_UAD,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
PDRIVE_PINGROUP_DAP5,
PDRIVE_PINGROUP_VBUS,
PDRIVE_PINGROUP_AO3,
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
enum pmux_drvgrp {
PMUX_DRVGRP_AO1,
PMUX_DRVGRP_AO2,
PMUX_DRVGRP_AT1,
PMUX_DRVGRP_AT2,
PMUX_DRVGRP_AT3,
PMUX_DRVGRP_AT4,
PMUX_DRVGRP_AT5,
PMUX_DRVGRP_CDEV1,
PMUX_DRVGRP_CDEV2,
PMUX_DRVGRP_DAP1 = (0x28 / 4),
PMUX_DRVGRP_DAP2,
PMUX_DRVGRP_DAP3,
PMUX_DRVGRP_DAP4,
PMUX_DRVGRP_DBG,
PMUX_DRVGRP_SDIO3 = (0x48 / 4),
PMUX_DRVGRP_SPI,
PMUX_DRVGRP_UAA,
PMUX_DRVGRP_UAB,
PMUX_DRVGRP_UART2,
PMUX_DRVGRP_UART3,
PMUX_DRVGRP_SDIO1 = (0x84 / 4),
PMUX_DRVGRP_DDC = (0x94 / 4),
PMUX_DRVGRP_GMA,
PMUX_DRVGRP_GME = (0xa8 / 4),
PMUX_DRVGRP_GMF,
PMUX_DRVGRP_GMG,
PMUX_DRVGRP_GMH,
PMUX_DRVGRP_OWR,
PMUX_DRVGRP_UDA,
PMUX_DRVGRP_GPV,
PMUX_DRVGRP_DEV3,
PMUX_DRVGRP_CEC = (0xd0 / 4),
PMUX_DRVGRP_AT6 = (0x12c / 4),
PMUX_DRVGRP_DAP5,
PMUX_DRVGRP_USB_VBUS_EN,
PMUX_DRVGRP_AO3 = (0x140 / 4),
PMUX_DRVGRP_AO0 = (0x148 / 4),
PMUX_DRVGRP_HV0,
PMUX_DRVGRP_SDIO4 = (0x15c / 4),
PMUX_DRVGRP_AO4,
PMUX_DRVGRP_COUNT,
};
/*
* Functions which can be assigned to each of the pin groups. The values here
* bear no relation to the values programmed into pinmux registers and are
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,
PMUX_FUNC_CRT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DAP3,
PMUX_FUNC_DAP4,
PMUX_FUNC_DAP5,
PMUX_FUNC_DISPA,
PMUX_FUNC_DISPB,
PMUX_FUNC_EMC_TEST0_DLL,
PMUX_FUNC_EMC_TEST1_DLL,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_INT,
PMUX_FUNC_HDMI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_IDE,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
PMUX_FUNC_OSC,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
PMUX_FUNC_PLLA_OUT,
PMUX_FUNC_PLLC_OUT1,
PMUX_FUNC_PLLM_OUT1,
PMUX_FUNC_PLLP_OUT2,
PMUX_FUNC_PLLP_OUT3,
PMUX_FUNC_PLLP_OUT4,
PMUX_FUNC_PWM,
PMUX_FUNC_PWR_INTR,
PMUX_FUNC_PWR_ON,
PMUX_FUNC_RTCK,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_TRACE,
PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
/* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK12,
PMUX_FUNC_DAP,
PMUX_FUNC_DAPSDMMC2,
PMUX_FUNC_DDR,
PMUX_FUNC_DEV3,
PMUX_FUNC_DISPLAYA,
PMUX_FUNC_DISPLAYA_ALT,
PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DP,
PMUX_FUNC_DTV,
PMUX_FUNC_VI_ALT1,
PMUX_FUNC_VI_ALT2,
PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
PMUX_FUNC_NAND_ALT,
PMUX_FUNC_POPSDIO4,
PMUX_FUNC_POPSDMMC4,
PMUX_FUNC_IRDA,
PMUX_FUNC_KBC,
PMUX_FUNC_OWR,
PMUX_FUNC_PE,
PMUX_FUNC_PE0,
PMUX_FUNC_PE1,
PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
PMUX_FUNC_PWRON,
PMUX_FUNC_RESET_OUT_N,
PMUX_FUNC_RTCK,
PMUX_FUNC_SATA,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
PMUX_FUNC_SOC,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
PMUX_FUNC_SYS,
PMUX_FUNC_TMDS,
PMUX_FUNC_TRACE,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_ULPI,
PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
/* End of Tegra3 MUX selectors */
PMUX_FUNC_USB,
PMUX_FUNC_SOC,
PMUX_FUNC_CPU,
PMUX_FUNC_CLK,
PMUX_FUNC_PWRON,
PMUX_FUNC_PMI,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
PMUX_FUNC_RSVD4 = 0x8003,
PMUX_FUNC_VI,
PMUX_FUNC_VI_ALT1,
PMUX_FUNC_VI_ALT3,
PMUX_FUNC_VIMCLK2,
PMUX_FUNC_VIMCLK2_ALT,
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
PMUX_FUNC_COUNT,
};
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) \
((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
(((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
/* return 1 if a pingrp is in range */
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* return 1 if a pin_pupd_is in range */
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
((pupd) <= PMUX_PULL_UP))
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
/* return 1 if a pin_tristate_is in range */
#define pmux_pin_tristate_isvalid(tristate) \
(((tristate) >= PMUX_TRI_NORMAL) && \
((tristate) <= PMUX_TRI_TRISTATE))
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
((io) <= PMUX_PIN_INPUT))
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
((lock) <= PMUX_PIN_LOCK_ENABLE))
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
((od) <= PMUX_PIN_OD_ENABLE))
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
#define PGRP_SLWR_MAX PGRP_SLWF_MAX
#define PGRP_DRVUP_NONE -1
#define PGRP_DRVUP_MAX 127
#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
#define PGRP_SCHMT_NONE -1
#define PGRP_HSM_NONE PGRP_SCHMT_NONE
/* return 1 if a padgrp is in range */
#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
/* return 1 if a slew-rate rising/falling edge value is in range */
#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
/* return 1 if a driver output pull-up/down strength code value is in range */
#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
/* return 1 if a low-power mode value is in range */
#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
/* Defines a pin group cfg's low-power mode select */
enum pgrp_lpmd {
PGRP_LPMD_X8 = 0,
PGRP_LPMD_X4,
PGRP_LPMD_X2,
PGRP_LPMD_X,
PGRP_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pgrp_schmt {
PGRP_SCHMT_DISABLE = 0,
PGRP_SCHMT_ENABLE = 1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pgrp_hsm {
PGRP_HSM_DISABLE = 0,
PGRP_HSM_ENABLE = 1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
struct padctrl_config {
enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
int slwf; /* falling edge slew */
int slwr; /* rising edge slew */
int drvup; /* pull-up drive strength */
int drvdn; /* pull-down drive strength */
enum pgrp_lpmd lpmd; /* low-power mode selection */
enum pgrp_schmt schmt; /* schmidt enable */
enum pgrp_hsm hsm; /* high-speed mode enable */
};
/* Tegra124 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
PDRIVE_PINGROUP_COUNT)
struct pmux_tri_ctlr {
uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
uint pmt_reserved5[PMUX_OFFSET];
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
};
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pingroup_config {
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
enum pmux_func func; /* function to assign FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
/* VIL/VIH receivers */
};
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the complete configuration for a pin group */
void pinmux_config_pingroup(struct pingroup_config *config);
/* Set a pin group to tristate or normal */
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
/**
* Configure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
/**
* Set the GP pad configs
*
* @param config List of config items
* @param len Number of config items in list
*/
void padgrp_config_table(struct padctrl_config *config, int len);
#endif /* _TEGRA124_PINMUX_H_ */
#endif /* _TEGRA124_PINMUX_H_ */

268
arch/arm/include/asm/arch-tegra124/usb.h
View file

@ -1,268 +0,0 @@
/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_USB_H_
#define _TEGRA124_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[2];
/* 0x130 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x140 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint reserved5_1;
/* 0x150 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6;
uint icusb_ctrl;
/* 0x160 */
uint ulpi_viewport;
uint reserved7;
uint reserved7_0;
uint reserved7_1;
/* 0x170 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x190 */
uint reserved9[8];
/* 0x1b0 */
uint reserved10;
uint hostpc1_devlc;
uint reserved10_1[2];
/* 0x1c0 */
uint reserved10_2[4];
/* 0x1d0 */
uint reserved10_3[4];
/* 0x1e0 */
uint reserved10_4[4];
/* 0x1f0 */
uint reserved10_5;
uint otgsc;
uint usb_mode;
uint reserved10_6;
/* 0x200 */
uint endpt_nak;
uint endpt_nak_enable;
uint endpt_setup_stat;
uint reserved11_1[0x7D];
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[3];
/* 0x420 */
uint reserved13[56];
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE 1
#define VBUS_SENSE_CTL_SHIFT 1
#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
#define VBUS_SENSE_CTL_AB_SESS_VLD 2
#define VBUS_SENSE_CTL_A_SESS_VLD 3
/* USBx_IF_USB_SUSP_CTRL_0 */
#define UTMIP_PHY_ENB (1 << 12)
#define UTMIP_RESET (1 << 11)
#define USB_PHY_CLK_VALID (1 << 7)
#define USB_SUSP_CLR (1 << 5)
/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/* Moved to Clock and Reset register space */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
#define UTMIP_PLLU_STABLE_COUNT_MASK \
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
/* Moved to Clock and Reset register space */
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
/* USBx_UTMIP_PLL_CFG1_0 */
/* Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
/* USBx_UTMIP_BIAS_CFG0_0 */
#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
#define UTMIP_OTGPD (1 << 11)
#define UTMIP_BIASPD (1 << 10)
#define UTMIP_HSDISCON_LEVEL_SHIFT 2
#define UTMIP_HSDISCON_LEVEL_MASK \
(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
#define UTMIP_HSSQUELCH_LEVEL_MASK \
(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
/* USBx_UTMIP_BIAS_CFG1_0 */
#define UTMIP_FORCE_PDTRK_POWERDOWN 1
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
#define UTMIP_BIAS_PDTRK_COUNT_MASK \
(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
/* USBx_UTMIP_TX_CFG0_0 */
#define UTMIP_FS_PREAMBLE_J (1 << 19)
/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
#define UTMIP_PD_CHRG 1
/* USBx_UTMIP_SPARE_CFG0_0 */
#define FUSE_SETUP_SEL (1 << 3)
/* USBx_UTMIP_HSRX_CFG0_0 */
#define UTMIP_IDLE_WAIT_SHIFT 15
#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
#define UTMIP_ELASTIC_LIMIT_SHIFT 10
#define UTMIP_ELASTIC_LIMIT_MASK \
(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
/* USBx_UTMIP_HSRX_CFG0_1 */
#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
#define UTMIP_HS_SYNC_START_DLY_MASK \
(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT 29
#define PTS_MASK (0x7U << PTS_SHIFT)
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2
#define PTS_ICUSB_SER 3
#define PTS_HSIC 4
#define STS (1 << 28)
/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
#define WKOC (1 << 22)
#define WKDS (1 << 21)
#define WKCN (1 << 20)
/* USBx_UTMIP_XCVR_CFG0_0 */
#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
#define UTMIP_XCVR_HSSLEW_MSB_MASK \
(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_SHIFT 0
#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
/* USBx_UTMIP_XCVR_CFG1_0 */
#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 << 26)
#endif /* _TEGRA124_USB_H_ */

352
arch/arm/include/asm/arch-tegra20/pinmux.h
View file

@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PINMUX_H_
#define _PINMUX_H_
#ifndef _TEGRA20_PINMUX_H_
#define _TEGRA20_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
@ -18,148 +18,146 @@
*/
enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
PINGRP_ATA,
PINGRP_ATB,
PINGRP_ATC,
PINGRP_ATD,
PINGRP_CDEV1,
PINGRP_CDEV2,
PINGRP_CSUS,
PINGRP_DAP1,
PMUX_PINGRP_ATA,
PMUX_PINGRP_ATB,
PMUX_PINGRP_ATC,
PMUX_PINGRP_ATD,
PMUX_PINGRP_CDEV1,
PMUX_PINGRP_CDEV2,
PMUX_PINGRP_CSUS,
PMUX_PINGRP_DAP1,
PINGRP_DAP2,
PINGRP_DAP3,
PINGRP_DAP4,
PINGRP_DTA,
PINGRP_DTB,
PINGRP_DTC,
PINGRP_DTD,
PINGRP_DTE,
PMUX_PINGRP_DAP2,
PMUX_PINGRP_DAP3,
PMUX_PINGRP_DAP4,
PMUX_PINGRP_DTA,
PMUX_PINGRP_DTB,
PMUX_PINGRP_DTC,
PMUX_PINGRP_DTD,
PMUX_PINGRP_DTE,
PINGRP_GPU,
PINGRP_GPV,
PINGRP_I2CP,
PINGRP_IRTX,
PINGRP_IRRX,
PINGRP_KBCB,
PINGRP_KBCA,
PINGRP_PMC,
PMUX_PINGRP_GPU,
PMUX_PINGRP_GPV,
PMUX_PINGRP_I2CP,
PMUX_PINGRP_IRTX,
PMUX_PINGRP_IRRX,
PMUX_PINGRP_KBCB,
PMUX_PINGRP_KBCA,
PMUX_PINGRP_PMC,
PINGRP_PTA,
PINGRP_RM,
PINGRP_KBCE,
PINGRP_KBCF,
PINGRP_GMA,
PINGRP_GMC,
PINGRP_SDIO1,
PINGRP_OWC,
PMUX_PINGRP_PTA,
PMUX_PINGRP_RM,
PMUX_PINGRP_KBCE,
PMUX_PINGRP_KBCF,
PMUX_PINGRP_GMA,
PMUX_PINGRP_GMC,
PMUX_PINGRP_SDIO1,
PMUX_PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
PINGRP_GME,
PINGRP_SDC,
PINGRP_SDD,
PINGRP_RESERVED0,
PINGRP_SLXA,
PINGRP_SLXC,
PINGRP_SLXD,
PINGRP_SLXK,
PMUX_PINGRP_GME,
PMUX_PINGRP_SDC,
PMUX_PINGRP_SDD,
PMUX_PINGRP_RESERVED0,
PMUX_PINGRP_SLXA,
PMUX_PINGRP_SLXC,
PMUX_PINGRP_SLXD,
PMUX_PINGRP_SLXK,
PINGRP_SPDI,
PINGRP_SPDO,
PINGRP_SPIA,
PINGRP_SPIB,
PINGRP_SPIC,
PINGRP_SPID,
PINGRP_SPIE,
PINGRP_SPIF,
PMUX_PINGRP_SPDI,
PMUX_PINGRP_SPDO,
PMUX_PINGRP_SPIA,
PMUX_PINGRP_SPIB,
PMUX_PINGRP_SPIC,
PMUX_PINGRP_SPID,
PMUX_PINGRP_SPIE,
PMUX_PINGRP_SPIF,
PINGRP_SPIG,
PINGRP_SPIH,
PINGRP_UAA,
PINGRP_UAB,
PINGRP_UAC,
PINGRP_UAD,
PINGRP_UCA,
PINGRP_UCB,
PMUX_PINGRP_SPIG,
PMUX_PINGRP_SPIH,
PMUX_PINGRP_UAA,
PMUX_PINGRP_UAB,
PMUX_PINGRP_UAC,
PMUX_PINGRP_UAD,
PMUX_PINGRP_UCA,
PMUX_PINGRP_UCB,
PINGRP_RESERVED1,
PINGRP_ATE,
PINGRP_KBCC,
PINGRP_RESERVED2,
PINGRP_RESERVED3,
PINGRP_GMB,
PINGRP_GMD,
PINGRP_DDC,
PMUX_PINGRP_RESERVED1,
PMUX_PINGRP_ATE,
PMUX_PINGRP_KBCC,
PMUX_PINGRP_RESERVED2,
PMUX_PINGRP_RESERVED3,
PMUX_PINGRP_GMB,
PMUX_PINGRP_GMD,
PMUX_PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
PINGRP_LD0,
PINGRP_LD1,
PINGRP_LD2,
PINGRP_LD3,
PINGRP_LD4,
PINGRP_LD5,
PINGRP_LD6,
PINGRP_LD7,
PMUX_PINGRP_LD0,
PMUX_PINGRP_LD1,
PMUX_PINGRP_LD2,
PMUX_PINGRP_LD3,
PMUX_PINGRP_LD4,
PMUX_PINGRP_LD5,
PMUX_PINGRP_LD6,
PMUX_PINGRP_LD7,
PINGRP_LD8,
PINGRP_LD9,
PINGRP_LD10,
PINGRP_LD11,
PINGRP_LD12,
PINGRP_LD13,
PINGRP_LD14,
PINGRP_LD15,
PMUX_PINGRP_LD8,
PMUX_PINGRP_LD9,
PMUX_PINGRP_LD10,
PMUX_PINGRP_LD11,
PMUX_PINGRP_LD12,
PMUX_PINGRP_LD13,
PMUX_PINGRP_LD14,
PMUX_PINGRP_LD15,
PINGRP_LD16,
PINGRP_LD17,
PINGRP_LHP0,
PINGRP_LHP1,
PINGRP_LHP2,
PINGRP_LVP0,
PINGRP_LVP1,
PINGRP_HDINT,
PMUX_PINGRP_LD16,
PMUX_PINGRP_LD17,
PMUX_PINGRP_LHP0,
PMUX_PINGRP_LHP1,
PMUX_PINGRP_LHP2,
PMUX_PINGRP_LVP0,
PMUX_PINGRP_LVP1,
PMUX_PINGRP_HDINT,
PINGRP_LM0,
PINGRP_LM1,
PINGRP_LVS,
PINGRP_LSC0,
PINGRP_LSC1,
PINGRP_LSCK,
PINGRP_LDC,
PINGRP_LCSN,
PMUX_PINGRP_LM0,
PMUX_PINGRP_LM1,
PMUX_PINGRP_LVS,
PMUX_PINGRP_LSC0,
PMUX_PINGRP_LSC1,
PMUX_PINGRP_LSCK,
PMUX_PINGRP_LDC,
PMUX_PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
PINGRP_LSPI,
PINGRP_LSDA,
PINGRP_LSDI,
PINGRP_LPW0,
PINGRP_LPW1,
PINGRP_LPW2,
PINGRP_LDI,
PINGRP_LHS,
PMUX_PINGRP_LSPI,
PMUX_PINGRP_LSDA,
PMUX_PINGRP_LSDI,
PMUX_PINGRP_LPW0,
PMUX_PINGRP_LPW1,
PMUX_PINGRP_LPW2,
PMUX_PINGRP_LDI,
PMUX_PINGRP_LHS,
PINGRP_LPP,
PINGRP_RESERVED4,
PINGRP_KBCD,
PINGRP_GPU7,
PINGRP_DTF,
PINGRP_UDA,
PINGRP_CRTP,
PINGRP_SDB,
PMUX_PINGRP_LPP,
PMUX_PINGRP_RESERVED4,
PMUX_PINGRP_KBCD,
PMUX_PINGRP_GPU7,
PMUX_PINGRP_DTF,
PMUX_PINGRP_UDA,
PMUX_PINGRP_CRTP,
PMUX_PINGRP_SDB,
/* these pin groups only have pullup and pull down control */
PINGRP_FIRST_NO_MUX,
PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
PINGRP_DDRC,
PINGRP_PMCA,
PINGRP_PMCB,
PINGRP_PMCC,
PINGRP_PMCD,
PINGRP_PMCE,
PINGRP_XM2C,
PINGRP_XM2D,
PINGRP_COUNT,
PMUX_PINGRP_CK32,
PMUX_PINGRP_DDRC,
PMUX_PINGRP_PMCA,
PMUX_PINGRP_PMCB,
PMUX_PINGRP_PMCC,
PMUX_PINGRP_PMCD,
PMUX_PINGRP_PMCE,
PMUX_PINGRP_XM2C,
PMUX_PINGRP_XM2D,
PMUX_PINGRP_COUNT,
};
/*
@ -227,111 +225,13 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
PMUX_FUNC_SAFE,
/* These don't have a name, but can be used in the table */
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
PMUX_FUNC_RSVD, /* Not valid and should not be used */
PMUX_FUNC_COUNT,
PMUX_FUNC_NONE = -1,
};
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
(func) != PMUX_FUNC_RSVD)
#include <asm/arch-tegra/pinmux.h>
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_NONE
};
enum {
PMUX_TRISTATE_REGS = 4,
PMUX_MUX_REGS = 7,
PMUX_PULL_REGS = 5,
};
/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
};
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pingroup_config {
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
enum pmux_func func; /* function to assign FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
};
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the complete configuration for a pin group */
void pinmux_config_pingroup(const struct pingroup_config *config);
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
/**
* Configuure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_table(const struct pingroup_config *config, int len);
#endif /* PINMUX_H */
#endif /* _TEGRA20_PINMUX_H_ */

155
arch/arm/include/asm/arch-tegra20/usb.h
View file

@ -1,155 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2013 NVIDIA Corporation
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA20_USB_H_
#define _TEGRA20_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[6];
/* 0x140 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x150 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint async_tt_sts;
/* 0x160 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6; /* is this port_sc1 on some controllers? */
uint icusb_ctrl;
/* 0x170 */
uint ulpi_viewport;
uint reserved7;
uint endpt_nak;
uint endpt_nak_enable;
/* 0x180 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x1a0 */
uint reserved9;
uint otgsc;
uint usb_mode;
uint endpt_setup_stat;
/* 0x1b0 */
uint reserved10[20];
/* 0x200 */
uint reserved11[0x80];
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[4];
/* 0x424 */
uint ulpi_timing_ctrl_0;
uint ulpi_timing_ctrl_1;
uint reserved13[53];
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB2_IF_ULPI_TIMING_CTRL_0 */
#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
/* USB2_IF_ULPI_TIMING_CTRL_1 */
#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
/* PORTSC, USB2, USB3 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
#define STS (1 << 29)
#endif /* _TEGRA20_USB_H_ */

965
arch/arm/include/asm/arch-tegra30/pinmux.h
View file

File diff suppressed because it is too large Load diff

168
arch/arm/include/asm/arch-tegra30/usb.h
View file

@ -1,168 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2013 NVIDIA Corporation
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA30_USB_H_
#define _TEGRA30_USB_H_
/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
/* 0x000 */
uint id;
uint reserved0;
uint host;
uint device;
/* 0x010 */
uint txbuf;
uint rxbuf;
uint reserved1[2];
/* 0x020 */
uint reserved2[56];
/* 0x100 */
u16 cap_length;
u16 hci_version;
uint hcs_params;
uint hcc_params;
uint reserved3[5];
/* 0x120 */
uint dci_version;
uint dcc_params;
uint reserved4[2];
/* 0x130 */
uint usb_cmd;
uint usb_sts;
uint usb_intr;
uint frindex;
/* 0x140 */
uint reserved5;
uint periodic_list_base;
uint async_list_addr;
uint reserved5_1;
/* 0x150 */
uint burst_size;
uint tx_fill_tuning;
uint reserved6;
uint icusb_ctrl;
/* 0x160 */
uint ulpi_viewport;
uint reserved7[3];
/* 0x170 */
uint reserved;
uint port_sc1;
uint reserved8[6];
/* 0x190 */
uint reserved9[8];
/* 0x1b0 */
uint reserved10;
uint hostpc1_devlc;
uint reserved10_1[2];
/* 0x1c0 */
uint reserved10_2[4];
/* 0x1d0 */
uint reserved10_3[4];
/* 0x1e0 */
uint reserved10_4[4];
/* 0x1f0 */
uint reserved10_5;
uint otgsc;
uint usb_mode;
uint reserved10_6;
/* 0x200 */
uint endpt_nak;
uint endpt_nak_enable;
uint endpt_setup_stat;
uint reserved11_1[0x7D];
/* 0x400 */
uint susp_ctrl;
uint phy_vbus_sensors;
uint phy_vbus_wakeup_id;
uint phy_alt_vbus_sys;
/* 0x410 */
uint usb1_legacy_ctrl;
uint reserved12[3];
/* 0x420 */
uint reserved13[56];
/* 0x500 */
uint reserved14[64 * 3];
/* 0x800 */
uint utmip_pll_cfg0;
uint utmip_pll_cfg1;
uint utmip_xcvr_cfg0;
uint utmip_bias_cfg0;
/* 0x810 */
uint utmip_hsrx_cfg0;
uint utmip_hsrx_cfg1;
uint utmip_fslsrx_cfg0;
uint utmip_fslsrx_cfg1;
/* 0x820 */
uint utmip_tx_cfg0;
uint utmip_misc_cfg0;
uint utmip_misc_cfg1;
uint utmip_debounce_cfg0;
/* 0x830 */
uint utmip_bat_chrg_cfg0;
uint utmip_spare_cfg0;
uint utmip_xcvr_cfg1;
uint utmip_bias_cfg1;
};
/* USB2_IF_ULPI_TIMING_CTRL_0 */
#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
/* USB2_IF_ULPI_TIMING_CTRL_1 */
#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT 29
#define PTS_MASK (0x7U << PTS_SHIFT)
#define STS (1 << 28)
#endif /* _TEGRA30_USB_H_ */

2
arch/arm/include/asm/config.h
View file

@ -7,6 +7,8 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH

2
arch/arm/include/asm/omap_common.h
View file

@ -574,6 +574,8 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
void usb_fake_mac_from_die_id(u32 *id);
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1

1
arch/arm/include/asm/u-boot.h
View file

@ -27,7 +27,6 @@
#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */

1
arch/arm/lib/board.c
View file

@ -445,7 +445,6 @@ void board_init_f(ulong bootflag)
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
gd->bd->bi_baudrate = gd->baudrate;
/* Ram ist board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */

1
arch/avr32/include/asm/u-boot.h
View file

@ -7,7 +7,6 @@
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;

1
arch/avr32/lib/board.c
View file

@ -220,7 +220,6 @@ void board_init_f(ulong board_type)
*/
bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
bd->bi_dram[0].size = sdram_size;
bd->bi_baudrate = gd->baudrate;
memcpy(new_gd, gd, sizeof(gd_t));

28
arch/blackfin/include/asm/net.h
View file

@ -1,28 +0,0 @@
/*
* net.h - misc Blackfin network helpers
*
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ASM_BFIN_RAND_MAC__
#define __ASM_BFIN_RAND_MAC__
/* If the board does not have a real MAC assigned to it, then generate a
* locally administrated pseudo-random one based on CYCLES and compile date.
*/
static inline void bfin_gen_rand_mac(uchar *mac_addr)
{
/* make something up */
const char s[] = __DATE__;
size_t i;
u32 cycles;
for (i = 0; i < 6; ++i) {
asm("%0 = CYCLES;" : "=r" (cycles));
mac_addr[i] = cycles ^ s[i];
}
mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
}
#endif

1
arch/blackfin/include/asm/u-boot.h
View file

@ -13,7 +13,6 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */

2
arch/blackfin/lib/board.c
View file

@ -69,7 +69,6 @@ static int display_banner(void)
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
gd->bd->bi_baudrate = gd->baudrate;
return 0;
}
@ -92,7 +91,6 @@ static void display_global_data(void)
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" \\-bd: %p\n", gd->bd);
printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
printf(" |-bi_memsize: %lx\n", bd->bi_memsize);

1
arch/m68k/include/asm/u-boot.h
View file

@ -44,7 +44,6 @@ typedef struct bd_info {
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */

1
arch/m68k/lib/board.c
View file

@ -342,7 +342,6 @@ board_init_f (ulong bootflag)
bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
#endif
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));

1
arch/microblaze/include/asm/u-boot.h
View file

@ -24,7 +24,6 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
ulong bi_boot_params; /* where this board expects params */
} bd_t;

1
arch/microblaze/lib/board.c
View file

@ -78,7 +78,6 @@ void board_init_f(ulong not_used)
memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */

2
arch/mips/include/asm/config.h
View file

@ -7,6 +7,8 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH

1
arch/mips/include/asm/u-boot.h
View file

@ -23,7 +23,6 @@
#else /* !CONFIG_SYS_GENERIC_BOARD */
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/mips/lib/board.c
View file

@ -204,7 +204,6 @@ void board_init_f(ulong bootflag)
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */
bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
memcpy(id, (void *)gd, sizeof(gd_t));

1
arch/nds32/include/asm/u-boot.h
View file

@ -23,7 +23,6 @@
#include <environment.h>
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/nds32/lib/board.c
View file

@ -255,7 +255,6 @@ void board_init_f(ulong bootflag)
addr_sp &= ~0x07;
debug("New Stack Pointer is: %08lx\n", addr_sp);
gd->bd->bi_baudrate = gd->baudrate;
/* Ram isn't board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */

1
arch/nios2/include/asm/u-boot.h
View file

@ -23,7 +23,6 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */

1
arch/nios2/lib/board.c
View file

@ -92,7 +92,6 @@ void board_init(void)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();

1
arch/openrisc/include/asm/u-boot.h
View file

@ -16,7 +16,6 @@
#define _U_BOOT_H_
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/openrisc/lib/board.c
View file

@ -84,7 +84,6 @@ void board_init(void)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
WATCHDOG_RESET();

2
arch/powerpc/cpu/mpc85xx/Makefile
View file

@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o

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