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ARM: tegra: enable PLLX only once it's been fully configured
This programming sequence is correct per Jimmy Zhang, and makes sense too! Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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1 changed files with 9 additions and 4 deletions
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@ -144,18 +144,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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reg |= (1 << PLL_DCCON_SHIFT);
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writel(reg, &pll->pll_misc);
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/* Enable PLLX */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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/* Disable BYPASS */
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reg = readl(&pll->pll_base);
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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debug("pllx_set_rate: base = 0x%08X\n", reg);
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/* Set lock_enable to PLLX_MISC */
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reg = readl(&pll->pll_misc);
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reg |= PLL_LOCK_ENABLE_MASK;
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writel(reg, &pll->pll_misc);
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debug("pllx_set_rate: misc = 0x%08X\n", reg);
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/* Enable PLLX last, once it's all configured */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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debug("pllx_set_rate: base final = 0x%08X\n", reg);
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return 0;
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}
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