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clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.5.3

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Synchronize R-Car R8A77990 E3 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-09-17 16:11:33 +02:00
parent f9ef870159
commit 41406bc988
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/renesas/r8a77990-cpg-mssr.c
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@ -52,7 +52,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a77990_core_clks[] = {
static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@ -132,7 +132,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
static const struct mssr_mod_clk r8a77990_mod_clks[] = {
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
@ -273,7 +273,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },