From 404bf4547ecb4c1409ae0936444fe02ba978e510 Mon Sep 17 00:00:00 2001 From: Alex Porosanu Date: Fri, 29 Apr 2016 15:17:59 +0300 Subject: [PATCH] arch/arm, arch/powerpc: add # of SEC engines on the SOC Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ board/freescale/c29xpcie/c29xpcie.c | 2 +- 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6529281c94..34b15007ea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -144,6 +144,7 @@ #define CONFIG_ARM_ERRATA_829520 #define CONFIG_ARM_ERRATA_833471 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -197,6 +198,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 92f30e28aa..139a623564 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -132,6 +132,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index eccc146dae..505d355bc8 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 +#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 #elif defined(CONFIG_QEMU_E500) #define CONFIG_MAX_CPUS 1 @@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif +#if !defined(CONFIG_PPC_C29X) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index e325b4db4a..45f463f01f 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset) while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET - + offset * 0x20000)) >= 0) { + + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) { fdt_del_node(blob, nodeoff); offset++; }