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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Blackfin: add driver for on-chip SPI controller
This fills out the SPI backend for the Blackfin on-chip SPI peripheral. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
7a1e87b106
commit
400f5778f3
2 changed files with 344 additions and 0 deletions
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@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libspi.a
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COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
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COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
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COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
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343
drivers/spi/bfin_spi.c
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343
drivers/spi/bfin_spi.c
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@ -0,0 +1,343 @@
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/*
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* Driver for Blackfin On-Chip SPI device
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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/*#define DEBUG*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/spi.h>
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struct bfin_spi_slave {
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struct spi_slave slave;
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void *mmr_base;
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u16 ctl, baud, flg;
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};
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#define MAKE_SPI_FUNC(mmr, off) \
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static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
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static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
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MAKE_SPI_FUNC(SPI_CTL, 0x00)
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MAKE_SPI_FUNC(SPI_FLG, 0x04)
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MAKE_SPI_FUNC(SPI_STAT, 0x08)
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MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
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MAKE_SPI_FUNC(SPI_RDBR, 0x10)
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MAKE_SPI_FUNC(SPI_BAUD, 0x14)
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#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
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__attribute__((weak))
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return (cs >= 1 && cs <= 7);
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}
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__attribute__((weak))
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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write_SPI_FLG(bss,
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(read_SPI_FLG(bss) &
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~((!bss->flg << 8) << slave->cs)) |
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(1 << slave->cs));
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debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
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}
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__attribute__((weak))
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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write_SPI_FLG(bss, read_SPI_FLG(bss) & ~(1 << slave->cs));
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debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
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}
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void spi_init()
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{
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct bfin_spi_slave *bss;
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u32 mmr_base;
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u32 baud;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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switch (bus) {
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#ifdef SPI_CTL
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# define SPI0_CTL SPI_CTL
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#endif
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case 0: mmr_base = SPI0_CTL; break;
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#ifdef SPI1_CTL
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case 1: mmr_base = SPI1_CTL; break;
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#endif
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#ifdef SPI2_CTL
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case 2: mmr_base = SPI2_CTL; break;
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#endif
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default: return NULL;
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}
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baud = get_sclk() / (2 * max_hz);
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if (baud < 2)
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baud = 2;
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else if (baud > (u16)-1)
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baud = -1;
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bss = malloc(sizeof(*bss));
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if (!bss)
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return NULL;
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bss->slave.bus = bus;
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bss->slave.cs = cs;
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bss->mmr_base = (void *)mmr_base;
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bss->ctl = SPE | MSTR | TDBR_CORE;
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if (mode & SPI_CPHA) bss->ctl |= CPHA;
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if (mode & SPI_CPOL) bss->ctl |= CPOL;
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if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
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bss->baud = baud;
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bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
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debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
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bus, cs, mmr_base, bss->ctl, baud, bss->flg);
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return &bss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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free(bss);
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}
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static void spi_portmux(struct spi_slave *slave)
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{
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#if defined(__ADSPBF51x__)
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#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
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u16 f_mux = bfin_read_PORTF_MUX();
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u16 f_fer = bfin_read_PORTF_FER();
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u16 g_mux = bfin_read_PORTG_MUX();
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u16 g_fer = bfin_read_PORTG_FER();
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u16 h_mux = bfin_read_PORTH_MUX();
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u16 h_fer = bfin_read_PORTH_FER();
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switch (slave->bus) {
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case 0:
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/* set SCK/MISO/MOSI */
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SET_MUX(g, 7, 1);
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g_fer |= PG12 | PG13 | PG14;
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switch (slave->cs) {
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case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
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case 2: /* see G above */ g_fer |= PG15; break;
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case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
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case 4: /* no muxing */ break;
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case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
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case 6: /* no muxing */ break;
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case 7: /* no muxing */ break;
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}
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case 1:
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/* set SCK/MISO/MOSI */
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SET_MUX(h, 0, 2);
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h_fer |= PH1 | PH2 | PH3;
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switch (slave->cs) {
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case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break;
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case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break;
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case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break;
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case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break;
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case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
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case 6: /* no muxing */ break;
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case 7: /* no muxing */ break;
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}
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}
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bfin_write_PORTF_MUX(f_mux);
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bfin_write_PORTF_FER(f_fer);
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bfin_write_PORTG_MUX(g_mux);
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bfin_write_PORTG_FER(g_fer);
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bfin_write_PORTH_MUX(h_mux);
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bfin_write_PORTH_FER(h_fer);
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#elif defined(__ADSPBF52x__)
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#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
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u16 f_mux = bfin_read_PORTF_MUX();
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u16 f_fer = bfin_read_PORTF_FER();
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u16 g_mux = bfin_read_PORTG_MUX();
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u16 g_fer = bfin_read_PORTG_FER();
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u16 h_mux = bfin_read_PORTH_MUX();
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u16 h_fer = bfin_read_PORTH_FER();
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/* set SCK/MISO/MOSI */
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SET_MUX(g, 0, 3);
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g_fer |= PG2 | PG3 | PG4;
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switch (slave->cs) {
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case 1: /* see G above */ g_fer |= PG1; break;
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case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
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case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
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case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break;
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case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break;
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case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break;
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case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
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}
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bfin_write_PORTF_MUX(f_mux);
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bfin_write_PORTF_FER(f_fer);
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bfin_write_PORTG_MUX(g_mux);
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bfin_write_PORTG_FER(g_fer);
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bfin_write_PORTH_MUX(h_mux);
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bfin_write_PORTH_FER(h_fer);
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#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
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u16 mux = bfin_read_PORT_MUX();
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u16 f_fer = bfin_read_PORTF_FER();
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u16 j_fer = bfin_read_PORTJ_FER();
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/* set SCK/MISO/MOSI */
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f_fer |= PF11 | PF12 | PF13;
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switch (slave->cs) {
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case 1: f_fer |= PF10; break;
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case 2: mux |= PJSE; j_fer |= PJ11; break;
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case 3: mux |= PJSE; j_fer |= PJ10; break;
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case 4: mux |= PFS4E; f_fer |= PF6; break;
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case 5: mux |= PFS5E; f_fer |= PF5; break;
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case 6: mux |= PFS6E; f_fer |= PF4; break;
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case 7: mux |= PJCE_SPI; j_fer |= PJ5; break;
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}
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bfin_write_PORT_MUX(mux);
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bfin_write_PORTF_FER(f_fer);
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bfin_write_PORTJ_FER(j_fer);
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#elif defined(__ADSPBF54x__)
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#define DO_MUX(port, pin) \
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mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
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fer |= P##port##pin;
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u32 mux;
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u16 fer;
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switch (slave->bus) {
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case 0:
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mux = bfin_read_PORTE_MUX();
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fer = bfin_read_PORTE_FER();
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/* set SCK/MISO/MOSI */
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DO_MUX(E, 0);
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DO_MUX(E, 1);
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DO_MUX(E, 2);
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switch (slave->cs) {
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case 1: DO_MUX(E, 4); break;
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case 2: DO_MUX(E, 5); break;
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case 3: DO_MUX(E, 6); break;
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}
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bfin_write_PORTE_MUX(mux);
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bfin_write_PORTE_FER(fer);
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break;
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case 1:
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mux = bfin_read_PORTG_MUX();
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fer = bfin_read_PORTG_FER();
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/* set SCK/MISO/MOSI */
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DO_MUX(G, 8);
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DO_MUX(G, 9);
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DO_MUX(G, 10);
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switch (slave->cs) {
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case 1: DO_MUX(G, 5); break;
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case 2: DO_MUX(G, 6); break;
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case 3: DO_MUX(G, 7); break;
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}
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bfin_write_PORTG_MUX(mux);
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bfin_write_PORTG_FER(fer);
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break;
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case 2:
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mux = bfin_read_PORTB_MUX();
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fer = bfin_read_PORTB_FER();
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/* set SCK/MISO/MOSI */
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DO_MUX(B, 12);
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DO_MUX(B, 13);
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DO_MUX(B, 14);
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switch (slave->cs) {
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case 1: DO_MUX(B, 9); break;
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case 2: DO_MUX(B, 10); break;
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case 3: DO_MUX(B, 11); break;
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}
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bfin_write_PORTB_MUX(mux);
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bfin_write_PORTB_FER(fer);
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break;
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}
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#endif
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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spi_portmux(slave);
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write_SPI_CTL(bss, bss->ctl);
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write_SPI_BAUD(bss, bss->baud);
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SSYNC();
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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write_SPI_CTL(bss, 0);
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SSYNC();
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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const u8 *tx = dout;
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u8 *rx = din;
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uint bytes = bitlen / 8;
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int ret = 0;
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
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slave->bus, slave->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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goto done;
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/* we can only do 8 bit transfers */
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if (bitlen % 8) {
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flags |= SPI_XFER_END;
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goto done;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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/* todo: take advantage of hardware fifos and setup RX dma */
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while (bytes--) {
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u8 value = (tx ? *tx++ : 0);
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debug("%s: tx:%x ", __func__, value);
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write_SPI_TDBR(bss, value);
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SSYNC();
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while ((read_SPI_STAT(bss) & TXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & SPIF))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & RXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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value = read_SPI_RDBR(bss);
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if (rx)
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*rx++ = value;
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debug("rx:%x\n", value);
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}
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done:
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return ret;
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}
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