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mx31: make HSP clock for mx3fb driver available
This additionally updates mx31/generic.c by - replacing __REG() macro accesses with readl() and writel() - providing macros for PDR0 and PLL bit accesses Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
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711a6722f9
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3f480bf7c3
3 changed files with 42 additions and 13 deletions
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@ -28,10 +28,10 @@
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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u32 mfi = (reg >> 10) & 0xf;
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u32 mfn = reg & 0x3ff;
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u32 mfd = (reg >> 16) & 0x3ff;
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u32 pd = (reg >> 26) & 0xf;
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u32 mfi = GET_PLL_MFI(reg);
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u32 mfn = GET_PLL_MFN(reg);
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u32 mfd = GET_PLL_MFD(reg);
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u32 pd = GET_PLL_PD(reg);
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mfi = mfi <= 5 ? 5 : mfi;
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mfd += 1;
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@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
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{
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u32 infreq;
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if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
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if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
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infreq = CONFIG_MX31_CLK32 * 1024;
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else
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infreq = CONFIG_MX31_HCLK_FREQ;
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return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
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return mx31_decode_pll(readl(CCM_MPCTL), infreq);
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}
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static u32 mx31_get_mcu_main_clk(void)
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@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void)
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static u32 mx31_get_ipg_clk(void)
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{
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u32 freq = mx31_get_mcu_main_clk();
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u32 pdr0 = __REG(CCM_PDR0);
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u32 pdr0 = readl(CCM_PDR0);
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freq /= ((pdr0 >> 3) & 0x7) + 1;
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freq /= ((pdr0 >> 6) & 0x3) + 1;
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freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
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freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
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return freq;
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}
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/* hsp is the clock for the ipu */
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static u32 mx31_get_hsp_clk(void)
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{
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u32 freq = mx31_get_mcu_main_clk();
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u32 pdr0 = readl(CCM_PDR0);
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freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
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return freq;
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}
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@ -77,6 +88,7 @@ void mx31_dump_clocks(void)
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u32 cpufreq = mx31_get_mcu_main_clk();
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printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
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printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
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printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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@ -89,6 +101,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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case MXC_CSPI_CLK:
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case MXC_UART_CLK:
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return mx31_get_ipg_clk();
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case MXC_IPU_CLK:
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return mx31_get_hsp_clk();
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}
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return -1;
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}
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@ -105,10 +119,10 @@ void mx31_gpio_mux(unsigned long mode)
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reg = IOMUXC_BASE + (mode & 0x1fc);
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shift = (~mode & 0x3) * 8;
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tmp = __REG(reg);
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tmp = readl(reg);
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tmp &= ~(0xff << shift);
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tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
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__REG(reg) = tmp;
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writel(tmp, reg);
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}
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void mx31_set_pad(enum iomux_pins pin, u32 config)
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@ -119,10 +133,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
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reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
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field = (pin + 2) % 3;
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l = __REG(reg);
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l = readl(reg);
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l &= ~(0x1ff << (field * 10));
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l |= config << (field * 10);
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__REG(reg) = l;
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writel(l, reg);
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}
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@ -30,6 +30,7 @@ enum mxc_clock {
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MXC_IPG_PERCLK,
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MXC_CSPI_CLK,
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MXC_UART_CLK,
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MXC_IPU_CLK
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};
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unsigned int mxc_get_clock(enum mxc_clock clk);
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@ -513,6 +513,20 @@ enum iomux_pins {
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
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#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
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#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
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#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
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#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
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#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
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#define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
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#define GET_PLL_PD(x) (((x) >> 26) & 0xf)
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#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
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#define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
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#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
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#define WEIM_ESDCTL0 0xB8001000
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#define WEIM_ESDCFG0 0xB8001004
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#define WEIM_ESDCTL1 0xB8001008
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