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https://github.com/AsahiLinux/u-boot
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i2c: designware_i2c: Prepare for DM driver conversion
This patch prepares the designware I2C driver for the DM conversion. This is mainly done by removing struct i2c_adapter from the functions that shall be used by the DM driver version as well. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Stefan Roese
Heiko Schocher
parent
11b544ab41
commit
3f4358da8d
1 changed files with 239 additions and 232 deletions
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@ -10,30 +10,6 @@
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#include <asm/io.h>
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#include "designware_i2c.h"
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static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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case 3:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
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#endif
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case 0:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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default:
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printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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{
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u32 ena = enable ? IC_ENABLE_0B : 0;
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@ -61,10 +37,9 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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*
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* Set the i2c speed.
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*/
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static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
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unsigned int speed)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int cntl;
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unsigned int hcnt, lcnt;
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int i2c_spd;
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@ -113,11 +88,243 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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/* Enable back i2c now speed set */
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dw_i2c_enable(i2c_base, true);
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adap->speed = speed;
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return 0;
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
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{
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/* Disable i2c */
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dw_i2c_enable(i2c_base, false);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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dw_i2c_enable(i2c_base, true);
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
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{
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
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{
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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return 1;
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
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int alen)
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{
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if (i2c_wait_for_bb(i2c_base))
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return 1;
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i2c_setaddress(i2c_base, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_regs *i2c_base)
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{
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb(i2c_base)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo(i2c_base);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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unsigned long start_time_rx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(i2c_base, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
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len--;
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start_time_rx = get_timer(0);
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return 1;
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}
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}
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return i2c_xfer_finish(i2c_base);
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Write to i2c memory.
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*/
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static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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int nb = len;
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unsigned long start_time_tx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(i2c_base, dev, addr, alen))
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return 1;
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start_time_tx = get_timer(0);
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while (len) {
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if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
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if (--len == 0) {
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writel(*buffer | IC_STOP,
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&i2c_base->ic_cmd_data);
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} else {
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writel(*buffer, &i2c_base->ic_cmd_data);
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}
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buffer++;
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start_time_tx = get_timer(0);
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} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
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printf("Timed out. i2c write Failed\n");
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return 1;
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}
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}
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return i2c_xfer_finish(i2c_base);
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}
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static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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case 3:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
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#endif
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case 0:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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default:
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printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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adap->speed = speed;
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return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
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}
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/*
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* i2c_init - Init function
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* @speed: required i2c speed
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@ -144,217 +351,16 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed,
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dw_i2c_enable(i2c_base, true);
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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/* Disable i2c */
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dw_i2c_enable(i2c_base, false);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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dw_i2c_enable(i2c_base, true);
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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return 1;
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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if (i2c_wait_for_bb(adap))
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return 1;
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i2c_setaddress(adap, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb(adap)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo(adap);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_rx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
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* address and the extra bits end up in the "chip address"
|
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(adap, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
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len--;
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start_time_rx = get_timer(0);
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return 1;
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}
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}
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return i2c_xfer_finish(adap);
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return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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||||
*
|
||||
* Write to i2c memory.
|
||||
*/
|
||||
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
|
||||
int alen, u8 *buffer, int len)
|
||||
{
|
||||
struct i2c_regs *i2c_base = i2c_get_base(adap);
|
||||
int nb = len;
|
||||
unsigned long start_time_tx;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
|
||||
|
||||
debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
|
||||
addr);
|
||||
#endif
|
||||
|
||||
if (i2c_xfer_init(adap, dev, addr, alen))
|
||||
return 1;
|
||||
|
||||
start_time_tx = get_timer(0);
|
||||
while (len) {
|
||||
if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
|
||||
if (--len == 0) {
|
||||
writel(*buffer | IC_STOP,
|
||||
&i2c_base->ic_cmd_data);
|
||||
} else {
|
||||
writel(*buffer, &i2c_base->ic_cmd_data);
|
||||
}
|
||||
buffer++;
|
||||
start_time_tx = get_timer(0);
|
||||
|
||||
} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
|
||||
printf("Timed out. i2c write Failed\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return i2c_xfer_finish(adap);
|
||||
return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -362,13 +368,14 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
|
|||
*/
|
||||
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
|
||||
{
|
||||
struct i2c_regs *i2c_base = i2c_get_base(adap);
|
||||
u32 tmp;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Try to read the first location of the chip.
|
||||
*/
|
||||
ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
|
||||
ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
|
||||
if (ret)
|
||||
dw_i2c_init(adap, adap->speed, adap->slaveaddr);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue