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riscv: dts: fix the mpfs's reference clock frequency

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The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
This commit is contained in:
Conor Dooley 2022-10-25 08:58:49 +01:00 committed by Leo Yu-Chi Liang
parent 4e405c68fb
commit 3f3527044d
2 changed files with 10 additions and 8 deletions
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4
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
View file

@ -54,6 +54,10 @@
};
};
&refclk {
clock-frequency = <125000000>;
};
&uart1 {
status = "okay";
};

14
arch/riscv/dts/microchip-mpfs.dtsi
View file

@ -170,6 +170,11 @@
};
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
@ -225,16 +230,9 @@
&cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "msspllclk";
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;