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fpga: xilinx: pass compatible flags to load() callback

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These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Oleksandr Suvorov 2022-07-22 17:16:10 +03:00 committed by Michal Simek
parent 71f1a5392a
commit 3e78481de9
8 changed files with 8 additions and 8 deletions
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2
drivers/fpga/spartan2.c
View file

@ -40,7 +40,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

2
drivers/fpga/spartan3.c
View file

@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

2
drivers/fpga/versalpl.c
View file

@ -27,7 +27,7 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len)
}
static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
ulong bin_buf;
int ret;

2
drivers/fpga/virtex2.c
View file

@ -83,7 +83,7 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
int ret_val = FPGA_FAIL;

2
drivers/fpga/xilinx.c
View file

@ -151,7 +151,7 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
return FPGA_FAIL;
}
return desc->operations->load(desc, buf, bsize, bstype);
return desc->operations->load(desc, buf, bsize, bstype, flags);
}
#if defined(CONFIG_CMD_FPGA_LOADFS)

2
drivers/fpga/zynqmppl.c
View file

@ -200,7 +200,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
}
static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap = 0;

2
drivers/fpga/zynqpl.c
View file

@ -371,7 +371,7 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
}
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
bitstream_type bstype, int flags)
{
unsigned long ts; /* Timestamp */
u32 isr_status, swap;

2
include/xilinx.h
View file

@ -53,7 +53,7 @@ typedef struct { /* typedef xilinx_desc */
struct xilinx_fpga_op {
int (*load)(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype);
bitstream_type bstype, int flags);
int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fpga_fsinfo);
int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize,