Merge branch '2022-12-23-complete-phase1-CONFIG-migration' into next

- Bring in the final series to complete the main portion of migrating CONFIG symbols to either Kconfig or CFG namespace (or removing / renaming entirely). With this, we have stricter CI tests as well now.
2025-03-16 06:46:59 +00:00 · 2022-12-23 22:19:39 -05:00 · 2022-12-23 22:19:39 -05:00 · 3e4cbe184a
commit 3e4cbe184a
parent 52d91e1c20 90c7888c9d
679 changed files with 1760 additions and 2325 deletions
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@ -53,37 +53,18 @@ stages:
            -j$(sysctl -n hw.logicalcpu)
        displayName: 'Perform tools-only build'

-  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for migrated symbols in board header'
+  - job: check_for_new_CONFIG_symbols_outside_Kconfig
+    displayName: 'Check for new CONFIG symbols outside Kconfig'
    pool:
      vmImage: $(ubuntu_vm)
    container:
      image: $(ci_runner_image)
      options: $(container_option)
    steps:
-      - script: |
-          KSYMLST=`mktemp`
-          KUSEDLST=`mktemp`
-          RET=0
-          cat `find . -name "Kconfig*"` | \
-             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             | sort -u > $KSYMLST
-          for CFG in `find include/configs -name "*.h"`; do
-             (grep '#define[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \
-                grep '#undef[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \
-                sort -u > ${KUSEDLST} || true
-             NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
-                cut -d , -f 3`
-             if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG:"
-                comm -12 ${KSYMLST} ${KUSEDLST}
-                RET=1
-             fi
-          done
-          exit $RET
+      # If grep succeeds and finds a match the test fails as we should
+      # have no matches.
+      - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+                  include/configs `find arch -name config.h` && exit 1 || exit 0

  - job: cppcheck
    displayName: 'Static code analysis with cppcheck'
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@ -124,31 +124,14 @@ build all other platforms:
        exit $ret;
      fi;

-check for migrated symbols in board header:
+check for new CONFIG symbols outside Kconfig:
  stage: testsuites
  script:
-    - KSYMLST=`mktemp`;
-      KUSEDLST=`mktemp`;
-      RET=0;
-      cat `find . -name "Kconfig*"` |
-         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         | sort -u > $KSYMLST;
-      for CFG in `find include/configs -name "*.h"`; do
-         (grep '#define[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ;
-            grep '#undef[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') |
-            sort -u > ${KUSEDLST} || true;
-         NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
-            cut -d , -f 3`;
-         if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG:";
-            comm -12 ${KSYMLST} ${KUSEDLST};
-            RET=1;
-         fi;
-      done;
-      exit $RET
+    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
+    # If grep succeeds and finds a match the test fails as we should
+    # have no matches.
+    - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+        include/configs `find arch -name config.h` && exit 1 || exit 0

 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
--- a/8
+++ b/8
@ -1075,10 +1075,6 @@ cmd_lzma = lzma -c -z -k -9 $< > $@

 cfg: u-boot.cfg

-quiet_cmd_cfgcheck = CFGCHK  $2
-cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
-		$(srctree)/scripts/config_whitelist.txt $(srctree)
-
 quiet_cmd_ofcheck = OFCHK   $2
 cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
 		$(srctree)/scripts/of_allowlist.txt
@ -1146,10 +1142,6 @@ endif
 	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
 	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
 	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(call cmd,cfgcheck,u-boot.cfg)
 	@# Check that this build does not override OF_HAS_PRIOR_STAGE by
 	@# disabling OF_BOARD.
 	$(call cmd,ofcheck,$(KCONFIG_CONFIG))
--- a/32
+++ b/32
@ -413,12 +413,12 @@ The following options need to be configured:
 					controller register space

 - Serial Ports:
-		CONFIG_PL011_CLOCK
+		CFG_PL011_CLOCK

 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.

-		CONFIG_PL01x_PORTS
+		CFG_PL01x_PORTS

 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
@ -541,13 +541,13 @@ The following options need to be configured:
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller

-			CONFIG_SH_ETHER_USE_PORT
+			CFG_SH_ETHER_USE_PORT
 			Define the number of ports to be used

-			CONFIG_SH_ETHER_PHY_ADDR
+			CFG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address

-			CONFIG_SH_ETHER_CACHE_WRITEBACK
+			CFG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.

 - TPM Support:
@ -843,7 +843,7 @@ The following options need to be configured:
 		CFG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.

-		CONFIG_SYS_I2C_DIRECT_BUS
+		CFG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
 		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
@ -855,7 +855,7 @@ The following options need to be configured:

 		CFG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
-		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
+		CFG_SYS_I2C_DIRECT_BUS is not defined, for example
 		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
 		CFG_SYS_NUM_I2C_BUSES = 9:

@ -955,7 +955,7 @@ The following options need to be configured:
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.

-		CONFIG_I2C_MULTI_BUS
+		CFG_I2C_MULTI_BUS

 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
@ -1018,7 +1018,7 @@ The following options need to be configured:
 		will require a board or device specific function to
 		be written.

-		CONFIG_FPGA_DELAY
+		CFG_FPGA_DELAY

 		If defined, a function that provides delays in the FPGA
 		configuration driver.
@ -1066,14 +1066,14 @@ The following options need to be configured:
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
-		or define CONFIG_ENV_FLAGS_LIST_STATIC.
+		or define CFG_ENV_FLAGS_LIST_STATIC.

 - Protected RAM:
-		CONFIG_PRAM
+		CFG_PRAM

 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
-		by U-Boot. Define CONFIG_PRAM to hold the number of
+		by U-Boot. Define CFG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
@ -1124,7 +1124,7 @@ The following options need to be configured:
 		symbols.

 - Default Environment:
-		CONFIG_EXTRA_ENV_SETTINGS
+		CFG_EXTRA_ENV_SETTINGS

 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
@ -1133,7 +1133,7 @@ The following options need to be configured:
 		For example, place something like this in your
 		board's config file:

-		#define CONFIG_EXTRA_ENV_SETTINGS \
+		#define CFG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"

@ -1405,7 +1405,7 @@ Configuration Settings:
 		Use buffered writes to flash.

 - CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
+- CFG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
@ -1436,7 +1436,7 @@ Configuration Settings:
 		Define this to a list (string) to define the ".flags"
 		environment variable in the default or embedded environment.

-	- CONFIG_ENV_FLAGS_LIST_STATIC
+	- CFG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -553,6 +553,9 @@ config ARM64_SUPPORT_AARCH32
 	help
 	  This ARM64 system supports AArch32 execution state.

+config IPROC
+	bool
+
 config S5P
 	def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX

@ -658,6 +661,7 @@ config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
+	select IPROC
 	imply BCM_SF2_ETH
 	imply BCM_SF2_ETH_GMAC
 	imply CMD_HASH
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry)
 ENDPROC(_do_nonsec_entry)

 .macro get_cbar_addr	addr
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
+#ifdef CFG_ARM_GIC_BASE_ADDRESS
+	ldr	\addr, =CFG_ARM_GIC_BASE_ADDRESS
 #else
 	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
 	bfc	\addr, #0, #15			@ clear reserved bits
@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)

-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
 WEAK(smp_waitloop)
 	wfi
-	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
+	ldr	r1, =CFG_SMP_PEN_ADDR	@ load start address
 	ldr	r1, [r1]
 #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
 	rev	r1, r1
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
@ -7,12 +7,11 @@

 #include <common.h>
 #include <errno.h>
-#include <pwm.h>
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>

-int pwm_enable(int pwm_id)
+int s5p_pwm_enable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@ -30,7 +29,7 @@ int pwm_enable(int pwm_id)
 	return 0;
 }

-void pwm_disable(int pwm_id)
+void s5p_pwm_disable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)

 #define NS_IN_SEC 1000000000UL

-int pwm_config(int pwm_id, int duty_ns, int period_ns)
+int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
 	return 0;
 }

-int pwm_init(int pwm_id, int div, int invert)
+int s5p_pwm_init(int pwm_id, int div, int invert)
 {
 	u32 val;
 	const struct s5p_timer *pwm =
@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert)
 		val |= TCON_INVERTER(pwm_id);
 	writel(val, &pwm->tcon);

-	pwm_enable(pwm_id);
+	s5p_pwm_enable(pwm_id);

 	return 0;
 }
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@ -16,10 +16,6 @@
 #include <asm/arch/clk.h>
 #include <linux/delay.h>

-/* Use the old PWM interface for now */
-#undef CONFIG_DM_PWM
-#include <pwm.h>
-
 DECLARE_GLOBAL_DATA_PTR;

 unsigned long get_current_tick(void);
@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void)
 int timer_init(void)
 {
 	/* PWM Timer 4 */
-	pwm_init(4, MUX_DIV_4, 0);
-	pwm_config(4, 100000, 100000);
-	pwm_enable(4);
+	s5p_pwm_init(4, MUX_DIV_4, 0);
+	s5p_pwm_config(4, 100000, 100000);
+	s5p_pwm_enable(4);

 	/* Use this as the current monotonic time in us */
 	gd->arch.timer_reset_value = 0;
--- a/arch/arm/cpu/armv7/s5p4418/cpu.c
+++ b/arch/arm/cpu/armv7/s5p4418/cpu.c
@ -64,7 +64,7 @@ static void serial_device_init(void)

 	/* set clock   */
 	clk_disable(clk);
-	clk_set_rate(clk, CONFIG_PL011_CLOCK);
+	clk_set_rate(clk, CFG_PL011_CLOCK);
 	clk_enable(clk);
 }
 #endif
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void)

 static unsigned long get_gicd_base_address(void)
 {
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#ifdef CFG_ARM_GIC_BASE_ADDRESS
+	return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
 #else
 	unsigned periphbase;

--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@ -29,6 +29,7 @@ config ARCH_LS1028A
 	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select FSL_TZASC_400
 	select GICV3
 	select NXP_LSCH3_2
 	select SYS_FSL_HAS_CCI400
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@ -1308,13 +1308,13 @@ phys_size_t get_effective_memsize(void)
 	 * allocated from first region. If the memory extends to  the second
 	 * region (or the third region if applicable), Management Complex (MC)
 	 * memory should be put into the highest region, i.e. the end of DDR
-	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
+	 * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
 	 * U-Boot doesn't relocate itself into higher address. Should DDR be
 	 * configured to skip the first region, this function needs to be
 	 * adjusted.
 	 */
-	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
-		ea_size = CONFIG_MAX_MEM_MAPPED;
+	if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
+		ea_size = CFG_MAX_MEM_MAPPED;
 		rem = gd->ram_size - ea_size;
 	} else {
 		ea_size = gd->ram_size;
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@ -36,7 +36,7 @@

 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE

 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0x06000000
@ -121,7 +121,7 @@

 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE

 /* DCFG - GUR */
 #define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
@ -147,7 +147,7 @@

 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE

 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@ -160,7 +160,6 @@

 #elif defined(CONFIG_ARCH_LS1028A)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
-#define CONFIG_FSL_TZASC_400

 /* TZ Protection Controller Definitions */
 #define TZPC_BASE				0x02200000
@ -191,7 +190,7 @@

 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE

 /* SEC */

@ -211,7 +210,7 @@
 #define CFG_SYS_NUM_FM1_DTSEC		7
 #define CFG_SYS_NUM_FM1_10GEC		1
 #define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE

 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1
@ -250,14 +249,14 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE

 #elif defined(CONFIG_ARCH_LS1046A)
 #define CFG_SYS_NUM_FMAN			1
 #define CFG_SYS_NUM_FM1_DTSEC		8
 #define CFG_SYS_NUM_FM1_10GEC		2
 #define CFG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE

 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@ -70,7 +70,7 @@
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 #ifdef CONFIG_DDR_SPD
-#define CONFIG_MAX_MEM_MAPPED			((phys_size_t)2 << 30)
+#define CFG_MAX_MEM_MAPPED			((phys_size_t)2 << 30)
 #endif

 #define DCU_LAYER_MAX_NUM			16
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@ -57,6 +57,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
 /**
 * Locations of the boot-device identifier in SRAM
 */
-#define BROM_BOOTSOURCE_ID_ADDR   (CONFIG_IRAM_BASE + 0x10)
+#define BROM_BOOTSOURCE_ID_ADDR   (CFG_IRAM_BASE + 0x10)

 #endif
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@ -8,10 +8,10 @@
 #include <asm/arch/cpu.h>

 #ifdef CONFIG_I2C0_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+#define CFG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
 #endif
 #ifdef CONFIG_I2C1_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+#define CFG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
 #endif
 #ifdef CONFIG_R_I2C_ENABLE
 #define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@ -8,9 +8,6 @@

 #include <linux/stringify.h>

-/* Architecture, CPU, chip, etc */
-#define CONFIG_IPROC
-
 /* Memory Info */
 #define CFG_SYS_SDRAM_BASE		0x61000000

--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@ -18,7 +18,7 @@
 /* EMAC */
 #ifdef CONFIG_KSNET_NETCP_V1_0

-#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define GBETH_BASE			(CFG_KSNET_NETCP_BASE + 0x00090000)
 #define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x900)
 #define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x300)
 #define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x100)
@ -32,7 +32,7 @@

 #elif defined CONFIG_KSNET_NETCP_V1_5

-#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define GBETH_BASE			(CFG_KSNET_NETCP_BASE + 0x00200000)
 #define CPGMACSL_REG_RX_PRI_MAP		0x020
 #define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x22000)
 #define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x00f00)
@ -49,7 +49,7 @@

 #define KEYSTONE2_EMAC_GIG_ENABLE

-#define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
+#define MAC_ID_BASE_ADDR		CFG_KSNET_MAC_ID_BASE

 /* MDIO module input frequency */
 #ifdef CONFIG_SOC_K2G
@ -117,7 +117,7 @@ struct mac_sl_cfg {
 #define CPSW_CTL_VLAN_AWARE			BIT(1)
 #define CPSW_CTL_FIFO_LOOPBACK			BIT(0)

-#define DEVICE_CPSW_NUM_PORTS			CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_CPSW_NUM_PORTS			CFG_KSNET_CPSW_NUM_PORTS
 #define DEVICE_N_GMACSL_PORTS			(DEVICE_CPSW_NUM_PORTS - 1)

 #ifdef CONFIG_KSNET_NETCP_V1_0
@ -190,14 +190,14 @@ struct mac_sl_cfg {
 /* PSS */
 #ifdef CONFIG_KSNET_NETCP_V1_0

-#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CFG_KSNET_NETCP_BASE + 0x604)
 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
 #define hw_config_streaming_switch()\
 	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);

 #elif defined CONFIG_KSNET_NETCP_V1_5

-#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CFG_KSNET_NETCP_BASE + 0x500)
 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0

 #define hw_config_streaming_switch()\
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@ -27,7 +27,7 @@ int dram_init(void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }

--- a/arch/arm/mach-exynos/include/mach/pwm.h
+++ b/arch/arm/mach-exynos/include/mach/pwm.h
@ -49,6 +49,11 @@ struct s5p_timer {
 	unsigned int	tcnto4;
 	unsigned int	tintcstat;
 };
+
+int s5p_pwm_init (int pwm_id, int div, int invert);
+int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns);
+int s5p_pwm_enable (int pwm_id);
+void s5p_pwm_disable (int pwm_id);
 #endif	/* __ASSEMBLY__ */

 #endif
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@ -51,7 +51,7 @@ enum {
 #ifdef CONFIG_EXYNOS5420

 /* Address for relocating helper code (Last 4 KB of IRAM) */
-#define EXYNOS_RELOCATE_CODE_BASE	(CONFIG_IRAM_TOP - 0x1000)
+#define EXYNOS_RELOCATE_CODE_BASE	(CFG_IRAM_TOP - 0x1000)

 /*
 * Power up secondary CPUs.
@ -73,14 +73,14 @@ static void low_power_start(void)

 	reg_val = readl(EXYNOS5420_SPARE_BASE);
 	if (reg_val != CPU_RST_FLAG_VAL) {
-		writel(0x0, CONFIG_LOWPOWER_FLAG);
+		writel(0x0, CFG_LOWPOWER_FLAG);
 		branch_bx(0x0);
 	}

-	reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
+	reg_val = readl(CFG_PHY_IRAM_BASE + 0x4);
 	if (reg_val != (uint32_t)&low_power_start) {
 		/* Store jump address as low_power_start if not present */
-		writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
+		writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4);
 		dsb();
 		sev();
 	}
@ -160,11 +160,11 @@ static void secondary_cores_configure(void)
 	writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));

 	/* set lowpower flag and address */
-	writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
-	writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
+	writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG);
+	writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR);
 	writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
 	/* Store jump address for power down */
-	writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
+	writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4);

 	/* Need all core power down check */
 	dsb();
--- a/arch/arm/mach-exynos/sec_boot.S
+++ b/arch/arm/mach-exynos/sec_boot.S
@ -21,7 +21,7 @@ relocate_wait_code:
 	.ltorg
 /*
 * Secondary core waits here until Primary wake it up.
- * Below code is copied to (CONFIG_IRAM_TOP - 0x1000)
+ * Below code is copied to (CFG_IRAM_TOP - 0x1000)
 * This is a workaround code which is supposed to act as a
 * substitute/supplement to the iROM code.
 *
--- a/arch/arm/mach-imx/syscounter.c
+++ b/arch/arm/mach-imx/syscounter.c
@ -65,7 +65,7 @@ int timer_init(void)
 	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
 	unsigned long val, freq;

-	freq = CONFIG_SC_TIMER_CLK;
+	freq = CFG_SC_TIMER_CLK;
 	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

 	writel(freq, &sctr->cntfid0);
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@ -24,7 +24,7 @@

 #include <asm/arch/soc.h>

-#define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
+#define CFG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
 #define MV_UART_CONSOLE_BASE	KW_UART0_BASE
 #define MV_SATA_BASE		KW_SATA_BASE
 #define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
@ -15,7 +15,7 @@
 #define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE

 /* TCLK Core Clock definition */
-#define CFG_SYS_TCLK			((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK			((readl(CFG_SAR_REG) & BIT(21)) ? \
 					166666667 : 200000000)

 #endif /* _ASM_ARCH_KW88F6281_H */
--- a/arch/arm/mach-kirkwood/include/mach/soc.h
+++ b/arch/arm/mach-kirkwood/include/mach/soc.h
@ -62,7 +62,7 @@
 #define MVCPU_WIN_ENABLE	KWCPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	KWCPU_WIN_DISABLE

-#define CONFIG_SAR_REG		(KW_MPP_BASE + 0x0030)
+#define CFG_SAR_REG		(KW_MPP_BASE + 0x0030)

 #if defined (CONFIG_KW88F6281)
 #include <asm/arch/kw88f6281.h>
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@ -83,7 +83,7 @@ u32 get_boot_device(void)
 	/*
 	 * Now check the SAR register for the strapped boot-device
 	 */
-	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */
+	val = readl(CFG_SAR_REG);	/* SAR - Sample At Reset */
 	boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
 	debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
 	switch (boot_device) {
@ -195,9 +195,9 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 	int i;

 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
-	val = readl(CONFIG_SAR2_REG);	/* SAR - Sample At Reset */
+	val = readl(CFG_SAR2_REG);	/* SAR - Sample At Reset */
 #else
-	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */
+	val = readl(CFG_SAR_REG);	/* SAR - Sample At Reset */
 #endif
 	freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
 #if defined(SAR2_CPU_FREQ_MASK)
@ -205,7 +205,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 	 * Shift CPU0 clock frequency select bit from SAR2 register
 	 * into correct position
 	 */
-	freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+	freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
 		 >> SAR2_CPU_FREQ_OFFS) << 3;
 #endif
 	for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@ -27,7 +27,4 @@

 #define MV_UART_CONSOLE_BASE		MVEBU_UART0_BASE

-/* Needed for SPI NOR booting in SPL */
-#define CONFIG_DM_SEQ_ALIAS		1
-
 #endif /* __MVEBU_CONFIG_H */
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@ -134,8 +134,8 @@

 #if defined(CONFIG_ARMADA_375)
 /* SAR values for Armada 375 */
-#define CONFIG_SAR_REG		(MVEBU_REGISTER(0xe8200))
-#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0xe8204))
+#define CFG_SAR_REG		(MVEBU_REGISTER(0xe8200))
+#define CFG_SAR2_REG		(MVEBU_REGISTER(0xe8204))

 #define SAR_CPU_FREQ_OFFS	17
 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
@ -146,11 +146,11 @@
 #define BOOT_FROM_UART		0x30
 #define BOOT_FROM_SPI		0x38

-#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK		((readl(CFG_SAR_REG) & BIT(20)) ? \
 				 200000000 : 166000000)
 #elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
-#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18600))
+#define CFG_SAR_REG		(MVEBU_REGISTER(0x18600))

 #define SAR_CPU_FREQ_OFFS	10
 #define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
@ -169,12 +169,12 @@
 #define BOOT_FROM_MMC		0x30
 #define BOOT_FROM_MMC_ALT	0x31

-#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK		((readl(CFG_SAR_REG) & BIT(15)) ? \
 				 200000000 : 250000000)
 #elif defined(CONFIG_ARMADA_MSYS)
 /* SAR values for MSYS */
-#define CONFIG_SAR_REG		(MBUS_DFX_BASE  + 0xf8200)
-#define CONFIG_SAR2_REG		(MBUS_DFX_BASE  + 0xf8204)
+#define CFG_SAR_REG		(MBUS_DFX_BASE  + 0xf8200)
+#define CFG_SAR2_REG		(MBUS_DFX_BASE  + 0xf8204)

 #define SAR_CPU_FREQ_OFFS	18
 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
@ -191,8 +191,8 @@
 #define CFG_SYS_TCLK		200000000	/* 200MHz */
 #elif defined(CONFIG_ARMADA_XP)
 /* SAR values for Armada XP */
-#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
-#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))
+#define CFG_SAR_REG		(MVEBU_REGISTER(0x18230))
+#define CFG_SAR2_REG		(MVEBU_REGISTER(0x18234))

 #define SAR_CPU_FREQ_OFFS	21
 #define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
--- a/arch/arm/mach-nexell/include/mach/pwm.h
+++ b/arch/arm/mach-nexell/include/mach/pwm.h
@ -49,6 +49,11 @@ struct s5p_timer {
 	unsigned int	tcnto4;
 	unsigned int	tintcstat;
 };
+
+int s5p_pwm_init (int pwm_id, int div, int invert);
+int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns);
+int s5p_pwm_enable (int pwm_id);
+void s5p_pwm_disable (int pwm_id);
 #endif	/* __ASSEMBLY__ */

 #endif
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@ -73,7 +73,7 @@ int dram_init(void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }

@ -521,7 +521,7 @@ void board_init_f(ulong dummy)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CFG_SYS_SDRAM_BASE,
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 }
 #endif

--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@ -203,7 +203,7 @@ u32 get_sec_mem_start(void)
 			omap_sdram_size()
 #else
 			get_ram_size((void *)CFG_SYS_SDRAM_BASE,
-				     CONFIG_MAX_RAM_BANK_SIZE)
+				     CFG_MAX_RAM_BANK_SIZE)
 #endif
 			- sec_mem_size));
 	return sec_mem_start;
--- a/arch/arm/mach-orion5x/dram.c
+++ b/arch/arm/mach-orion5x/dram.c
@ -39,7 +39,7 @@ int dram_init (void)
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(long *) orion5x_sdram_bar(0),
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	return 0;
 }

@ -51,7 +51,7 @@ int dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
 		gd->bd->bi_dram[i].size = get_ram_size(
 			(long *) (gd->bd->bi_dram[i].start),
-			CONFIG_MAX_RAM_BANK_SIZE);
+			CFG_MAX_RAM_BANK_SIZE);
 	}

 	return 0;
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@ -53,7 +53,7 @@
 #define MVCPU_WIN_ENABLE	ORION5X_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	ORION5X_WIN_DISABLE

-#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
+#define CFG_MAX_RAM_BANK_SIZE		(64*1024*1024)

 /* include here SoC variants. 5181, 5281, 6183 should go here when
   adding support for them, and this comment should then be updated. */
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@ -168,9 +168,6 @@ config SPL_LIBGENERIC_SUPPORT
 config SPL_SERIAL
 	default y

-config TPL_LDSCRIPT
-	default "arch/arm/mach-rockchip/u-boot-tpl.lds"
-
 config TPL_STACK
        default 0xff718000

--- a/arch/arm/mach-rockchip/u-boot-tpl.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl.lds
@ -1,12 +0,0 @@
-// SPDX-License-Identifier:	GPL-2.0+
-/*
- * Copyright (C) 2019 Rockchip Electronic Co.,Ltd
- */
-
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
-
-#undef CONFIG_SPL_MAX_SIZE
-#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
-
-#include "../cpu/u-boot-spl.lds"
--- a/arch/arm/mach-s5pc1xx/include/mach/pwm.h
+++ b/arch/arm/mach-s5pc1xx/include/mach/pwm.h
@ -49,6 +49,11 @@ struct s5p_timer {
 	unsigned int	tcnto4;
 	unsigned int	tintcstat;
 };
+
+int s5p_pwm_init (int pwm_id, int div, int invert);
+int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns);
+int s5p_pwm_enable (int pwm_id);
+void s5p_pwm_disable (int pwm_id);
 #endif	/* __ASSEMBLY__ */

 #endif
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@ -89,7 +89,7 @@ int checkboard(void)
 {
 	int board_id = tegra_board_id();

-	printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
+	printf("Board: %s", CFG_TEGRA_BOARD_STRING);
 	if (board_id != -1)
 		printf(", ID: %d\n", board_id);
 	printf("\n");
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@ -200,6 +200,9 @@ config FSL_SERDES
 	bool "SerDes initialization"
 	depends on !MPC83XX_SERDES

+config NEVER_ASSERT_ODT_TO_CPU
+	bool "Never assert ODT to internal IOs"
+
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"

--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@ -931,7 +931,7 @@ config ARCH_T4240
 	imply FSL_SATA

 config MPC85XX_HAVE_RESET_VECTOR
-	bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
+	bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
 	depends on MPC85xx

 config BTB
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@ -357,7 +357,7 @@ void
 init_85xx_watchdog(void)
 {
 	mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
-	      TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+	      TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
 }

 void
@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 /*
 * slide the testing window up to test another area
 * for 32_bit system, the maximum testable memory is limited to
- * CONFIG_MAX_MEM_MAPPED
+ * CFG_MAX_MEM_MAPPED
 */
 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
 	phys_addr_t test_cap, p_addr;
-	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+	phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);

 #if !defined(CONFIG_PHYS_64BIT) || \
    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 #endif
 	p_addr = (*vstart) + (*size) + (*phys_offset);
 	if (p_addr < test_cap - 1) {
-		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
+		p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
 		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 			return -1;
 		*vstart = CFG_SYS_DDR_SDRAM_BASE;
@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 /* initialization for testing area */
 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+	phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);

 	*vstart = CFG_SYS_DDR_SDRAM_BASE;
-	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
+	*size = (u32) p_size;	/* CFG_MAX_MEM_MAPPED < 4G */
 	*phys_offset = 0;

 #if !defined(CONFIG_PHYS_64BIT) || \
    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
 	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
-		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+		if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
 			puts("Cannot test more than ");
-			print_size(CONFIG_MAX_MEM_MAPPED,
+			print_size(CFG_MAX_MEM_MAPPED,
 				" without proper 36BIT support.\n");
 		}
 #endif
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize)


 	/* use last 4K of mapped memory */
-	bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
-		CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+	bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ?
+		CFG_MAX_MEM_MAPPED : gd->ram_size) +
 		CFG_SYS_SDRAM_BASE - 4096;
 	if (pagesize)
 		*pagesize = 4096;
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
 #endif
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
 #if defined(CONFIG_ARCH_T1024)
 	rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
 #else
@ -215,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif

 #ifdef CONFIG_SYS_DPAA_PME
-#ifndef CONFIG_PME_PLAT_CLK_DIV
+#ifndef CFG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
@ -249,10 +249,10 @@ void get_sys_info(sys_info_t *sys_info)
 #endif

 #ifdef CONFIG_SYS_DPAA_QBMAN
-#ifndef CONFIG_QBMAN_CLK_DIV
-#define CONFIG_QBMAN_CLK_DIV	2
+#ifndef CFG_QBMAN_CLK_DIV
+#define CFG_QBMAN_CLK_DIV	2
 #endif
-	sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
+	sys_info->freq_qman = sys_info->freq_systembus / CFG_QBMAN_CLK_DIV;
 #endif

 #if defined(CONFIG_SYS_MAPLE)
@ -377,7 +377,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif

 #ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_FM_PLAT_CLK_DIV
+#ifndef CFG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
 	u64 memsize = (u64)memsize_in_meg << 20;
 	u64 size;

-	size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
+	size = min(memsize, (u64)CFG_MAX_MEM_MAPPED);
 	size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);

-	if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
-		print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
-			   memsize - CONFIG_MAX_MEM_MAPPED + size : size,
+	if (size || memsize > CFG_MAX_MEM_MAPPED) {
+		print_size(memsize > CFG_MAX_MEM_MAPPED ?
+			   memsize - CFG_MAX_MEM_MAPPED + size : size,
 			   " of DDR memory left unmapped in U-Boot\n");
 #ifndef CONFIG_SPL_BUILD
 		puts("       ");
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@ -5,8 +5,8 @@

 #include "config.h"

-#ifdef CONFIG_RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS	CONFIG_RESET_VECTOR_ADDRESS
+#ifdef CFG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	CFG_RESET_VECTOR_ADDRESS
 #else
 #define RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)

 	tbl->start_addr[i] =
 			(uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
-	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
+	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED));
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;

 	i++;
--- a/arch/powerpc/dts/kmcent2-u-boot.dtsi
+++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi
@ -91,7 +91,7 @@
 			align = <256>;
 		};
 		powerpc-mpc85xx-bootpg-resetvec {
-			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+			offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
 		};
 	};
 };
--- a/arch/powerpc/dts/u-boot.dtsi
+++ b/arch/powerpc/dts/u-boot.dtsi
@ -23,11 +23,11 @@
 		u-boot-dtb-with-ucode {
 			align = <4>;
 		};
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 		powerpc-mpc85xx-bootpg-resetvec {
-			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+			offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
 		};
 	};
 };
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@ -14,13 +14,13 @@
  #define HWCONFIG_BUFFER_SIZE 256
 #endif

-#ifndef CONFIG_MAX_MEM_MAPPED
+#ifndef CFG_MAX_MEM_MAPPED
 #if	defined(CONFIG_E500)		|| \
 	defined(CONFIG_MPC86xx)		|| \
 	defined(CONFIG_E300)
-#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
+#define CFG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
-#define CONFIG_MAX_MEM_MAPPED	(256 << 20)
+#define CFG_MAX_MEM_MAPPED	(256 << 20)
 #endif
 #endif

--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@ -144,11 +144,11 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_PME_PLAT_CLK_DIV		2
-#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_PME_PLAT_CLK_DIV		2
+#define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_FM_PLAT_CLK_DIV	1
-#define CFG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CFG_FM_PLAT_CLK_DIV	1
+#define CFG_SYS_FM1_CLK		CFG_FM_PLAT_CLK_DIV
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@ -163,7 +163,7 @@
 #define CFG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_QBMAN_CLK_DIV		1
+#define CFG_QBMAN_CLK_DIV		1
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@ -182,8 +182,8 @@
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #endif
-#define CONFIG_PME_PLAT_CLK_DIV		1
-#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_PME_PLAT_CLK_DIV		1
+#define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@ -535,7 +535,7 @@ int sandbox_main(int argc, char *argv[])
 	}

 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
-	gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+	gd->malloc_base = CFG_MALLOC_F_ADDR;
 #endif
 #if CONFIG_IS_ENABLED(LOG)
 	gd->default_log_level = state->default_log_level;
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@ -35,7 +35,7 @@ SECTIONS
 	.text :
 	{
 		KEEP(*/start.o		(.text))
-		KEEP(CONFIG_BOARDDIR/lowlevel_init.o	(.text .spiboot1.text))
+		KEEP(CFG_BOARDDIR/lowlevel_init.o	(.text .spiboot1.text))
 		KEEP(*(.spiboot2.text))
 		. = ALIGN(8192);
 #ifdef CONFIG_ENV_IS_IN_FLASH
--- a/arch/x86/cpu/broadwell/refcode.c
+++ b/arch/x86/cpu/broadwell/refcode.c
@ -78,7 +78,7 @@ static int cpu_run_reference_code(void)
 	int ret, dummy;
 	int size;

-	hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR;
+	hdr = (struct rmodule_header *)CFG_X86_REFCODE_ADDR;
 	debug("Extracting code from rmodule at %p\n", hdr);
 	if (hdr->magic != RMODULE_MAGIC) {
 		debug("Invalid rmodule magic\n");
@ -99,7 +99,7 @@ static int cpu_run_reference_code(void)
 	pei_data->saved_data = (void *)&dummy;

 	src = (char *)hdr + hdr->payload_begin_offset;
-	dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR;
+	dest = (char *)CFG_X86_REFCODE_RUN_ADDR;

 	size = hdr->payload_end_offset - hdr->payload_begin_offset;
 	debug("Copying refcode from %p to %p, size %x\n", src, dest, size);
@ -112,7 +112,7 @@ static int cpu_run_reference_code(void)
 	func = (asmlinkage int (*)(void *))dest;
 	debug("Running reference code at %p\n", func);
 #ifdef DEBUG
-	print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0);
+	print_buffer(CFG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0);
 #endif
 	ret = func(pei_data);
 	if (ret != 0) {
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@ -200,7 +200,7 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,

 	debug("PEI data at %p:\n", pei_data);

-	data = (char *)CONFIG_X86_MRC_ADDR;
+	data = (char *)CFG_X86_MRC_ADDR;
 	if (data) {
 		int rv;
 		ulong start;
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@ -86,7 +86,7 @@
 #endif
 #ifdef CONFIG_HAVE_MRC
 	intel-mrc {
-		offset = <CONFIG_X86_MRC_ADDR>;
+		offset = <CFG_X86_MRC_ADDR>;
 	};
 #endif
 #ifdef CONFIG_FSP_VERSION1
@ -149,7 +149,7 @@
 #endif
 #ifdef CONFIG_HAVE_REFCODE
 	intel-refcode {
-		offset = <CONFIG_X86_REFCODE_ADDR>;
+		offset = <CFG_X86_REFCODE_ADDR>;
 	};
 #endif
 #ifdef CONFIG_TPL
--- a/arch/xtensa/include/asm/config.h
+++ b/arch/xtensa/include/asm/config.h
@ -14,7 +14,7 @@
 * restricting used physical memory to the first 128MB.
 */
 #if XCHAL_HAVE_PTP_MMU
-#define CONFIG_MAX_MEM_MAPPED (128 << 20)
+#define CFG_MAX_MEM_MAPPED (128 << 20)
 #endif

 #endif
--- a/board/armltd/total_compute/total_compute.c
+++ b/board/armltd/total_compute/total_compute.c
@ -13,7 +13,7 @@
 static const struct pl01x_serial_plat serial_plat = {
 	.base = UART0_BASE,
 	.type = TYPE_PL011,
-	.clock = CONFIG_PL011_CLOCK,
+	.clock = CFG_PL011_CLOCK,
 };

 U_BOOT_DRVINFO(total_compute_serials) = {
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct pl01x_serial_plat serial_plat = {
 	.base = V2M_UART0,
 	.type = TYPE_PL011,
-	.clock = CONFIG_PL011_CLOCK,
+	.clock = CFG_PL011_CLOCK,
 };

 U_BOOT_DRVINFO(vexpress_serials) = {
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@ -89,7 +89,7 @@ int misc_init_r(void)
 	char *s = env_get("ethaddr");
 	if (s == 0) {
 		unsigned int x;
-		char s[] = __stringify(CONFIG_ETHBASE);
+		char s[] = __stringify(CFG_ETHBASE);
 		x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW)
 			& FPGAREG_MAC_MASK;
 		sprintf(&s[15], "%02x", x);
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@ -214,7 +214,7 @@ int board_eth_init(struct bd_info *bis)
 	gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
 	/* MAC initialization */
 	return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
-				       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+				       CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 }

 /*
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@ -160,7 +160,7 @@ int board_eth_init(struct bd_info *bis)
 	/* Set peripheral pins. */
 	at91_macb_hw_init();
 	/* Basic EMAC initialization. */
-	if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
+	if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CFG_PHY_ID))
 		return -1;
 	/*
 	 * Early board revisions have a pull-down at the PHY's MODE0
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@ -163,7 +163,7 @@ int checkboard(void)
 	u_char hw_type;	/* hardware type */

 	/* read the "Type" register of the ET1100 controller */
-	hw_type = readb(CONFIG_ET1100_BASE);
+	hw_type = readb(CFG_ET1100_BASE);

 	switch (hw_type) {
 	case 0x11:
--- a/board/freescale/common/i2c_common.c
+++ b/board/freescale/common/i2c_common.c
@ -9,7 +9,7 @@
 #include <i2c.h>
 #include "i2c_common.h"

-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)

 /* If DM is in use, retrieve the chip for the specified bus number */
 int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev)
--- a/board/freescale/common/i2c_common.h
+++ b/board/freescale/common/i2c_common.h
@ -9,7 +9,7 @@
 #define __NXP_I2C_COMMON_H__

 /* Common functionality shared by the I2C drivers for VID and the mux. */
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
 #define DEVICE_HANDLE_T struct udevice *

 #define I2C_READ(dev, register, data, length) \
--- a/board/freescale/common/ics307_clk.c
+++ b/board/freescale/common/ics307_clk.c
@ -50,7 +50,7 @@ static u8 ics307_s_to_od[] = {
 */
 unsigned long ics307_sysclk_calculator(unsigned long out_freq)
 {
-	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
 	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
 	unsigned long tmp_out, diff, result = 0;
 	int found = 0;
@ -101,7 +101,7 @@ unsigned long ics307_sysclk_calculator(unsigned long out_freq)
 */
 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
 {
-	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
 	unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 	unsigned long rdw = cw2 & 0x7F;
 	unsigned long od = ics307_s_to_od[cw0 & 0x7];
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@ -146,19 +146,19 @@ int board_early_init_f(void)
 	/* we check only part num, and don't look for CPU revisions */
 	switch (PARTID_NO_E(spridr)) {
 	case SPR_8377:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+		fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+		fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 		break;
 	case SPR_8378:
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+		fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 		break;
 	case SPR_8379:
-		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+		fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+		fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 		break;
 	default:
@ -206,9 +206,9 @@ int misc_init_r(void)
 {
 	int rc = 0;

-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
+#ifdef CFG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE,
+		CFG_VSC7385_IMAGE_SIZE)) {
 		puts("Failure uploading VSC7385 microcode.\n");
 		rc = 1;
 	}
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@ -86,7 +86,7 @@ static void power_init(void)
 	struct pmic *p;
 	int ret;

-	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+	ret = pmic_init(CFG_FSL_PMIC_BUS);
 	if (ret)
 		return;

--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis)
 	setup_fec();

 	ret = fecmxc_initialize_multi(bis, 1,
-		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+		CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 	if (ret)
 		printf("FEC%d MXC: %s:failed\n", 1, __func__);

--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@ -281,7 +281,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

 #ifdef	CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+	setup_fec(CFG_FEC_ENET_DEV);
 #endif

 #ifdef CONFIG_USB_EHCI_MX6
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@ -110,7 +110,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

 #ifdef	CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+	setup_fec(CFG_FEC_ENET_DEV);
 #endif

 	return 0;
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@ -57,7 +57,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc

 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@ -187,7 +187,7 @@ void board_gpio_init(void)
 	setbits_be32(&pgpio->gpdat, 0x00080000);
 #endif

-#ifdef CONFIG_SLIC
+#ifdef CFG_SLIC
 	/* reset SLIC */
 	setbits_be32(&pgpio->gpdir, 0x00040000);
 	setbits_be32(&pgpio->gpdat, 0x00040000);
@ -355,7 +355,7 @@ int board_early_init_r(void)
 		vscfw_addr = hextoul(tmp, NULL);
 		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
 		if (vsc7385_upload_firmware((void *)vscfw_addr,
-					    CONFIG_VSC7385_IMAGE_SIZE))
+					    CFG_VSC7385_IMAGE_SIZE))
 			puts("Failure uploading VSC7385 microcode.\n");
 	} else {
 		puts("No address specified for VSC7385 microcode.\n");
--- a/board/freescale/p2041rdb/README
+++ b/board/freescale/p2041rdb/README
@ -98,7 +98,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc

 CPLD command
 ============
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@ -379,7 +379,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc

 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@ -285,7 +285,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc

 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@ -281,7 +281,7 @@ enabled in relative defconfig file,
 1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
 2. CONFIG_OF_CONTROL
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+   CFG_RESET_VECTOR_ADDRESS - 0xffc

 If device tree support is enabled in defconfig,
 1. use 'u-boot.bin' for NOR boot.
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c
@ -80,9 +80,9 @@ static void bd_backlight_on(void)

 #elif defined(BACKLIGHT_CH)
 	/* pwm backlight ON: HIGH, ON: LOW */
-	pwm_init(BACKLIGHT_CH,
+	s5p_pwm_init(BACKLIGHT_CH,
 		 BACKLIGHT_DIV, BACKLIGHT_INV);
-	pwm_config(BACKLIGHT_CH,
+	s5p_pwm_config(BACKLIGHT_CH,
 		   TO_DUTY_NS(BACKLIGHT_DUTY, BACKLIGHT_HZ),
 		   TO_PERIOD_NS(BACKLIGHT_HZ));
 #endif
--- a/board/friendlyarm/nanopi2/onewire.c
+++ b/board/friendlyarm/nanopi2/onewire.c
@ -9,8 +9,8 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pwm.h>
 #include <i2c.h>
-#include <pwm.h>

 #include <irq_func.h>

@ -102,7 +102,7 @@ static int onewire_init_timer(void)
 	/* range: 1080~1970 */
 	period_ns -= 1525;

-	return pwm_config(PWM_CH, period_ns >> 1, period_ns);
+	return s5p_pwm_config(PWM_CH, period_ns >> 1, period_ns);
 }

 static void wait_one_tick(void)
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@ -791,8 +791,8 @@ void setup_pmic(void)
 	i2c_set_bus_num(i2c_pmic);

 	/* configure PFUZE100 PMIC */
-	if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
-		debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
+	if (!i2c_probe(CFG_POWER_PFUZE100_I2C_ADDR)) {
+		debug("probed PFUZE100@0x%x\n", CFG_POWER_PFUZE100_I2C_ADDR);
 		power_pfuze100_init(i2c_pmic);
 		p = pmic_get("PFUZE100");
 		if (p && !pmic_probe(p)) {
@ -851,8 +851,8 @@ void setup_pmic(void)
 	}

 	/* configure LTC3676 PMIC */
-	else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
-		debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
+	else if (!i2c_probe(CFG_POWER_LTC3676_I2C_ADDR)) {
+		debug("probed LTC3676@0x%x\n", CFG_POWER_LTC3676_I2C_ADDR);
 		power_ltc3676_init(i2c_pmic);
 		p = pmic_get("LTC3676_PMIC");
 		if (!p || pmic_probe(p))
--- a/board/ge/b1x5v2/spl.c
+++ b/board/ge/b1x5v2/spl.c
@ -565,9 +565,9 @@ void board_init_f(ulong dummy)
 	timer_init();

 	/* iomux */
-	if (CONFIG_MXC_UART_BASE == UART2_BASE)
+	if (CFG_MXC_UART_BASE == UART2_BASE)
 		SETUP_IOMUX_PADS(uart2_pads);
-	else if (CONFIG_MXC_UART_BASE == UART3_BASE)
+	else if (CFG_MXC_UART_BASE == UART3_BASE)
 		SETUP_IOMUX_PADS(uart3_pads);

 	/* UART clocks enabled and gd valid - init serial console */
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@ -216,8 +216,8 @@ int post_hotkeys_pressed(void)
 	int testpin = 0;
 	struct km_bec_fpga *base =
 		(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
-	int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
-	testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
+	int testpin_reg = in_8(&base->CFG_TESTPIN_REG);
+	testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0;
 	debug("post_hotkeys_pressed: %d\n", !testpin);
 	return testpin;
 }
--- a/board/keymile/kmcent2/kmcent2.env
+++ b/board/keymile/kmcent2/kmcent2.env
@ -10,9 +10,9 @@ hostname=kmcent2
 hwconfig=fsl_ddr:ctlr_intlv=cacheline
 netdev=eth2

-newenv=protect off ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE  &&
-       erase ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE &&
-       protect on ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE
+newenv=protect off ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE  &&
+       erase ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE &&
+       protect on ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE

 set_fdthigh=true
 uimage=uImage
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c
@ -167,7 +167,7 @@ void sdram_init(void)

 	/* Detect memory physically present */
 	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
-				    CONFIG_MAX_RAM_BANK_SIZE);
+				    CFG_MAX_RAM_BANK_SIZE);

 	/* Reconfigure memory for actual detected size */
 	switch (gd->ram_size) {
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@ -322,6 +322,8 @@ void disable_charger_bq25895(void)
 }

 #define I2C_PMIC	0
+#define POWER_BD71837_I2C_BUS	0
+#define POWER_BD71837_I2C_ADDR	0x4B

 int power_bd71837_init(unsigned char bus)
 {
@ -336,7 +338,7 @@ int power_bd71837_init(unsigned char bus)
 	p->name = name;
 	p->interface = I2C_PMIC;
 	p->number_of_regs = BD718XX_MAX_REGISTER;
-	p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR;
+	p->hw.i2c.addr = POWER_BD71837_I2C_ADDR;
 	p->hw.i2c.tx_num = 1;
 	p->bus = bus;

@ -357,10 +359,10 @@ int power_init_board(void)
 	/*
 	 * Init PMIC
 	 */
-	rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS);
+	rv = power_bd71837_init(POWER_BD71837_I2C_BUS);
 	if (rv) {
 		log_err("%s: power_bd71837_init(%d) error %d\n", __func__,
-			CONFIG_POWER_BD71837_I2C_BUS, rv);
+			POWER_BD71837_I2C_BUS, rv);
 		goto out;
 	}

--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@ -112,10 +112,10 @@ int checkboard(void)
 }
 #endif

-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
-	writel(addr, CONFIG_SMP_PEN_ADDR);
+	writel(addr, CFG_SMP_PEN_ADDR);

 	/* make sure this write is really executed */
 	__asm__ volatile ("dsb\n");
--- a/board/samsung/common/exynos5-dt-types.c
+++ b/board/samsung/common/exynos5-dt-types.c
@ -57,7 +57,7 @@ static int odroid_get_adc_val(unsigned int *adcval)
 	unsigned int adcval_prev = 0;
 	int ret, retries = 20;

-	ret = adc_channel_single_shot("adc@12D10000", CONFIG_ODROID_REV_AIN,
+	ret = adc_channel_single_shot("adc@12D10000", CFG_ODROID_REV_AIN,
 				      &adcval_prev);
 	if (ret)
 		return ret;
@ -66,7 +66,7 @@ static int odroid_get_adc_val(unsigned int *adcval)
 		mdelay(5);

 		ret = adc_channel_single_shot("adc@12D10000",
-					      CONFIG_ODROID_REV_AIN, adcval);
+					      CFG_ODROID_REV_AIN, adcval);
 		if (ret)
 			return ret;

--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@ -179,9 +179,9 @@ char *get_dfu_alt_boot(char *interface, char *devstr)
 		return NULL;

 	if (IS_SD(mmc))
-		alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+		alt_boot = CFG_DFU_ALT_BOOT_SD;
 	else
-		alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+		alt_boot = CFG_DFU_ALT_BOOT_EMMC;

 	return alt_boot;
 }
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SET_DFU_ALT_INFO
 void set_dfu_alt_info(char *interface, char *devstr)
 {
-	size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
+	size_t buf_size = CFG_SET_DFU_ALT_BUF_LEN;
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
 	char *alt_info = "Settings not found!";
 	char *status = "error!\n";
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@ -94,8 +94,8 @@ char *get_dfu_alt_boot(char *interface, char *devstr)
 	if (mmc_init(mmc))
 		return NULL;

-	alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
-				CONFIG_DFU_ALT_BOOT_EMMC;
+	alt_boot = IS_SD(mmc) ? CFG_DFU_ALT_BOOT_SD :
+				CFG_DFU_ALT_BOOT_EMMC;

 	return alt_boot;
 }
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@ -25,16 +25,16 @@ static void smc9115_pre_init(void)
 	u32 smc_bw_conf, smc_bc_conf;

 	/* gpio configuration GPK0CON */
-	gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(S5PC100_GPIO_K00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));

 	/* Ethernet needs bus width of 16 bits */
-	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bw_conf = SMC_DATA16_WIDTH(CFG_ENV_SROM_BANK);
 	smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
 			| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
 			| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);

 	/* Select and configure the SROMC bank */
-	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+	s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
 }

 int board_init(void)
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@ -24,17 +24,17 @@ static void smc9115_pre_init(void)
 	u32 smc_bw_conf, smc_bc_conf;

 	/* gpio configuration GPK0CON */
-	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));

 	/* Ethernet needs bus width of 16 bits */
-	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bw_conf = SROMC_DATA16_WIDTH(CFG_ENV_SROM_BANK);
 	smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
 			| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
 			| SROMC_BC_TAH(0x0F)  | SROMC_BC_TACP(0x0F)
 			| SROMC_BC_PMC(0x0F);

 	/* Select and configure the SROMC bank */
-	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+	s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
 }

 int board_init(void)
--- a/board/seeed/npi_imx6ull/npi_imx6ull.c
+++ b/board/seeed/npi_imx6ull/npi_imx6ull.c
@ -100,7 +100,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

 #ifdef CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+	setup_fec(CFG_FEC_ENET_DEV);
 #endif

 	return 0;
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@ -277,13 +277,13 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	case DRA752_ES2_0:
 		switch (emif_nr) {
 		case 1:
-			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+			if (ram_size > CFG_MAX_MEM_MAPPED)
 				*regs = &emif1_ddr3_532_mhz_1cs_2G;
 			else
 				*regs = &emif1_ddr3_532_mhz_1cs;
 			break;
 		case 2:
-			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+			if (ram_size > CFG_MAX_MEM_MAPPED)
 				*regs = &emif2_ddr3_532_mhz_1cs_2G;
 			else
 				*regs = &emif2_ddr3_532_mhz_1cs;
@ -301,7 +301,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
 	case DRA722_ES2_1:
-		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+		if (ram_size < CFG_MAX_MEM_MAPPED)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 		else
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
@ -360,7 +360,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
-		if (ram_size > CONFIG_MAX_MEM_MAPPED)
+		if (ram_size > CFG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_dra7_2GB;
 		else
 			*dmm_lisa_regs = &lisa_map_dra7_1536MB;
@ -369,7 +369,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	case DRA722_ES2_0:
 	case DRA722_ES2_1:
 	default:
-		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+		if (ram_size < CFG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_2G_x_2;
 		else
 			*dmm_lisa_regs = &lisa_map_2G_x_4;
@ -644,9 +644,9 @@ int dram_init_banksize(void)

 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
-	if (ram_size > CONFIG_MAX_MEM_MAPPED) {
+	if (ram_size > CFG_MAX_MEM_MAPPED) {
 		gd->bd->bi_dram[1].start = 0x200000000;
-		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
+		gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
 	}

 	return 0;
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@ -47,7 +47,7 @@ int dram_init(void)
 	ddr3_size = ddr3_init();

 	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
-				    CONFIG_MAX_RAM_BANK_SIZE);
+				    CFG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
 	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
 		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
--- a/board/variscite/dart_6ul/dart_6ul.c
+++ b/board/variscite/dart_6ul/dart_6ul.c
@ -147,7 +147,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

 #ifdef CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+	setup_fec(CFG_FEC_ENET_DEV);
 #endif

 #ifdef CONFIG_NAND_MXS
--- a/boot/Kconfig
+++ b/boot/Kconfig
@ -36,10 +36,9 @@ config TIMESTAMP
 	  loaded that does not, the message 'Wrong FIT format: no timestamp'
 	  is shown.

-if FIT
-
 config FIT_EXTERNAL_OFFSET
 	hex "FIT external data offset"
+	depends on FIT
 	default 0x0
 	help
 	  This specifies a data offset in fit image.
@ -50,6 +49,7 @@ config FIT_EXTERNAL_OFFSET

 config FIT_FULL_CHECK
 	bool "Do a full check of the FIT before using it"
+	depends on FIT
 	default y
 	help
 	  Enable this do a full check of the FIT to make sure it is valid. This
@ -59,7 +59,7 @@ config FIT_FULL_CHECK

 config FIT_SIGNATURE
 	bool "Enable signature verification of FIT uImages"
-	depends on DM
+	depends on DM && FIT
 	select HASH
 	imply RSA
 	imply RSA_VERIFY
@ -97,7 +97,7 @@ config FIT_RSASSA_PSS

 config FIT_CIPHER
 	bool "Enable ciphering data in a FIT uImages"
-	depends on DM
+	depends on DM && FIT
 	select AES
 	help
 	  Enable the feature of data ciphering/unciphering in the tool mkimage
@ -105,6 +105,7 @@ config FIT_CIPHER

 config FIT_VERBOSE
 	bool "Show verbose messages when FIT images fail"
+	depends on FIT
 	help
 	  Generally a system will have valid FIT images so debug messages
 	  are a waste of code space. If you are debugging your images then
@ -113,6 +114,7 @@ config FIT_VERBOSE

 config FIT_BEST_MATCH
 	bool "Select the best match for the kernel device tree"
+	depends on FIT
 	help
 	  When no configuration is explicitly selected, default to the
 	  one whose fdt's compatibility field best matches that of
@ -122,6 +124,7 @@ config FIT_BEST_MATCH

 config FIT_IMAGE_POST_PROCESS
 	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+	depends on FIT
 	depends on TI_SECURE_DEVICE || SOCFPGA_SECURE_VAB_AUTH
 	default y if TI_SECURE_DEVICE
 	help
@ -137,15 +140,14 @@ config FIT_IMAGE_POST_PROCESS

 config FIT_PRINT
        bool "Support FIT printing"
+	depends on FIT
        default y
        help
          Support printing the content of the fitImage in a verbose manner.

-if SPL
-
 config SPL_FIT
 	bool "Support Flattened Image Tree within SPL"
-	depends on SPL
+	depends on SPL && FIT
 	select SPL_HASH
 	select SPL_OF_LIBFDT

@ -157,13 +159,13 @@ config SPL_FIT_PRINT

 config SPL_FIT_FULL_CHECK
 	bool "Do a full check of the FIT before using it"
+	depends on SPL_FIT
 	help
 	  Enable this do a full check of the FIT to make sure it is valid. This
 	  helps to protect against carefully crafted FITs which take advantage
 	  of bugs or omissions in the code. This includes a bad structure,
 	  multiple root nodes and the like.

-
 config SPL_FIT_SIGNATURE
 	bool "Enable signature verification of FIT firmware within SPL"
 	depends on SPL_DM
@ -196,6 +198,7 @@ config SPL_FIT_RSASSA_PSS

 config SPL_LOAD_FIT
 	bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
+	depends on SPL && FIT
 	select SPL_FIT
 	help
 	  Normally with the SPL framework a legacy image is generated as part
@ -217,7 +220,7 @@ config SPL_LOAD_FIT

 config SPL_LOAD_FIT_ADDRESS
 	hex "load address of fit image"
-	depends on SPL_LOAD_FIT
+	depends on SPL_LOAD_FIT || SPL_RAM_SUPPORT || TPL_RAM_SUPPORT
 	default 0x0
 	help
 	  Specify the load address of the fit image that will be loaded
@ -243,6 +246,7 @@ config SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ

 config SPL_LOAD_FIT_FULL
 	bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
+	depends on FIT
 	select SPL_FIT
 	help
 	  Normally with the SPL framework a legacy image is generated as part
@ -277,7 +281,8 @@ config SPL_FIT_SOURCE

 config USE_SPL_FIT_GENERATOR
 	bool "Use a script to generate the .its script"
-	default y if SPL_FIT && (!ARCH_SUNXI && !RISCV)
+	depends on SPL_FIT
+	default y if !ARCH_SUNXI && !RISCV

 config SPL_FIT_GENERATOR
 	string ".its file generator script for U-Boot FIT image"
@ -290,8 +295,6 @@ config SPL_FIT_GENERATOR
 	  passed a list of supported device tree file stub names to
 	  include in the generated image.

-endif # SPL
-
 if VPL

 config VPL_FIT
@ -342,8 +345,6 @@ config VPL_FIT_SIGNATURE_MAX_SIZE

 endif # VPL

-endif # FIT
-
 config PXE_UTILS
 	bool
 	select MENU
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@ -577,8 +577,8 @@ cleanup:
 		free(command);
 	}

-#ifdef CONFIG_POSTBOOTMENU
-	run_command(CONFIG_POSTBOOTMENU, 0);
+#ifdef CFG_POSTBOOTMENU
+	run_command(CFG_POSTBOOTMENU, 0);
 #endif

 	if (efi_ret != EFI_SUCCESS || cmd_ret != CMD_RET_SUCCESS)
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@ -1699,7 +1699,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,

 		for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) {
 			printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
 			int j;

 			for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
@ -1735,7 +1735,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
 			return -1;
 		}
 		printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
 			int j;
 			for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
 				if (i2c_bus[i].next_hop[j].chip == 0)
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@ -130,8 +130,8 @@ static int qemu_fwcfg_do_load(struct cmd_tbl *cmdtp, int flag,
 	env = env_get("ramdiskaddr");
 	initrd_addr = env ?
 		(void *)hextoul(env, NULL) :
-#ifdef CONFIG_RAMDISK_ADDR
-		(void *)CONFIG_RAMDISK_ADDR;
+#ifdef CFG_RAMDISK_ADDR
+		(void *)CFG_RAMDISK_ADDR;
 #else
 		NULL;
 #endif
--- a/common/board_f.c
+++ b/common/board_f.c
@ -380,19 +380,19 @@ static int setup_dest_addr(void)
 	return arch_setup_dest_addr();
 }

-#ifdef CONFIG_PRAM
+#ifdef CFG_PRAM
 /* reserve protected RAM */
 static int reserve_pram(void)
 {
 	ulong reg;

-	reg = env_get_ulong("pram", 10, CONFIG_PRAM);
+	reg = env_get_ulong("pram", 10, CFG_PRAM);
 	gd->relocaddr -= (reg << 10);		/* size is in kB */
 	debug("Reserving %ldk for protected RAM at %08lx\n", reg,
 	      gd->relocaddr);
 	return 0;
 }
-#endif /* CONFIG_PRAM */
+#endif /* CFG_PRAM */

 /* Round memory pointer down to next 4 kB limit */
 static int reserve_round_4k(void)
@ -925,7 +925,7 @@ static const init_fnc_t init_sequence_f[] = {
 #ifdef CONFIG_OF_BOARD_FIXUP
 	fix_fdt,
 #endif
-#ifdef CONFIG_PRAM
+#ifdef CFG_PRAM
 	reserve_pram,
 #endif
 	reserve_round_4k,
--- a/Show more
+++ b/Show more