Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+	puts("Work-around for Erratum A004508 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	puts("Work-around for Erratum A004510 enabled\n");
 #endif
@@ -266,6 +269,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 	puts("Work-around for Erratum USB14 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	puts("Work-around for Erratum A007186 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 	puts("Work-around for Erratum A006593 enabled\n");
 #endif

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
 }
 #endif
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+	int ret;
+	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+	int tdm_hwconfig_enabled = 0;
+
+	/*
+	 * Extract hwconfig from environment since environment
+	 * is not setup properly yet. Search for tdm entry in
+	 * hwconfig.
+	 */
+	ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (ret > 0) {
+		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+		/* If tdm is defined in hwconfig, set law for tdm workaround */
+		if (tdm_hwconfig_enabled)
+			set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+				     LAW_TRGT_IF_CCSR);
+	}
+}
+#endif
+
 static void enable_cpc(void)
 {
 	int i;
@@ -729,6 +755,9 @@ skip_l2:
 	disable_cpc_sram();
 #endif
 	enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+	enable_tdm_law();
+#endif
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	/* needs to be in ram since code uses global static vars */

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -14,6 +14,7 @@
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_portals.h>
+#include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 id = get_my_id();
 	const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+	int ret;
+	int tdm_hwconfig_enabled = 0;
+	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
 
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 				"device_type", "cpu", 4);
 	}
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define	CONFIG_MEM_HOLE_16M	0x1000000
+	/*
+	 * Extract hwconfig from environment.
+	 * Search for tdm entry in hwconfig.
+	 */
+	ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (ret > 0)
+		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+	/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+	if (tdm_hwconfig_enabled) {
+		off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+				      CONFIG_MEM_HOLE_16M);
+		if (off < 0)
+			printf("Failed  to reserve memory for tdm: %s\n",
+			       fdt_strerror(off));
+	}
+#endif
+
 	/* Reserve the boot page so OSes dont use it */
 	if ((u64)bootpg < memory_limit) {
 		off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -147,12 +147,43 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	return -ENODEV;
 }
 
+#define BC3_SHIFT	9
+#define DC3_SHIFT	6
+#define FC3_SHIFT	0
+#define BC2_SHIFT	19
+#define DC2_SHIFT	16
+#define FC2_SHIFT	10
+#define BC1_SHIFT	29
+#define DC1_SHIFT	26
+#define FC1_SHIFT	20
+#define BC_MASK		0x1
+#define DC_MASK		0x7
+#define FC_MASK		0x3F
+
+#define FUSE_VAL_MASK		0x00000003
+#define FUSE_VAL_SHIFT		30
+#define CR0_DCBIAS_SHIFT	5
+#define CR1_FCAP_SHIFT		15
+#define CR1_BCAP_SHIFT		29
+#define FCAP_MASK		0x001F8000
+#define BCAP_MASK		0x20000000
+#define BCAP_OVD_MASK		0x10000000
+#define BYP_CAL_MASK		0x02000000
+
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	struct ccsr_sfp_regs  __iomem *sfp_regs =
+			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+	u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+	u32 bc_status, fc_status, dc_status, pll_sr2;
+	serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
+	u32 sfp_spfr0, sel;
+#endif
 
 	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
 	/* Is serdes enabled at all? */
@@ -161,6 +192,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		return 0;
 	}
 
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+	debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+	sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+	if (sel == 0x01 || sel == 0x02) {
+		for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+			pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			debug("A007186: pll_num=%x pllcr0=%x\n",
+			      pll_num, pll_status);
+			/* STEP 1 */
+			/* Read factory pre-set SerDes calibration values
+			 * from fuse block(SFP scratch register-sfp_spfr0)
+			 */
+			switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+			case SRDS_PLLCR0_FRATE_SEL_3_0:
+			case SRDS_PLLCR0_FRATE_SEL_3_072:
+				debug("A007186: 3.0/3.072 protocol rate\n");
+				bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+				break;
+			case SRDS_PLLCR0_FRATE_SEL_3_125:
+				debug("A007186: 3.125 protocol rate\n");
+				bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+				break;
+			case SRDS_PLLCR0_FRATE_SEL_3_75:
+				debug("A007186: 3.75 protocol rate\n");
+				bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+				break;
+			default:
+				continue;
+			}
+
+			/* STEP 2 */
+			/* Write SRDSxPLLnCR1[11:16] = FC
+			 * Write SRDSxPLLnCR1[2] = BC
+			 */
+			pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+			pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+				      ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+				 (pll_cr_upd | pll_cr1));
+			debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+			      pll_num, (pll_cr_upd | pll_cr1));
+			/* Write SRDSxPLLnCR0[24:26] = DC
+			 */
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0,
+				 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+			debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+			      pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+			/* Write SRDSxPLLnCR1[3] = 1
+			 * Write SRDSxPLLnCR1[6] = 1
+			 */
+			pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+			pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+				 (pll_cr_upd | pll_cr1));
+			debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+			      pll_num, (pll_cr_upd | pll_cr1));
+
+			/* STEP 3 */
+			/* Read the status Registers */
+			/* Verify SRDSxPLLnSR2[8] = BC */
+			pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+			debug("A007186: pll_num=%x pllsr2=%x\n",
+			      pll_num, pll_sr2);
+			bc_status = (pll_sr2 >> 23) & BC_MASK;
+			if (bc_status != bc)
+				debug("BC mismatch\n");
+			fc_status = (pll_sr2 >> 16) & FC_MASK;
+			if (fc_status != fc)
+				debug("FC mismatch\n");
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+								0x02000000);
+			pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+			dc_status = (pll_sr2 >> 17) & DC_MASK;
+			if (dc_status != dc)
+				debug("DC mismatch\n");
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+								0xfdffffff);
+
+			/* STEP 4 */
+			/* Wait 750us to verify the PLL is locked
+			 * by checking SRDSxPLLnCR0[8] = 1.
+			 */
+			udelay(750);
+			pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			debug("A007186: pll_num=%x pllcr0=%x\n",
+			      pll_num, pll_status);
+
+			if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+				printf("A007186 Serdes PLL not locked\n");
+			else
+				debug("A007186 Serdes PLL locked\n");
+		}
+	}
+#endif
+
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 	if (!is_serdes_prtcl_valid(sd, cfg))

arch/powerpc/cpu/mpc85xx/t1040_ids.c

@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
 
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
 	SET_QE_LIODN(559),
+	SET_TDM_LIODN(560),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 

arch/powerpc/cpu/mpc85xx/t2080_serdes.c

@@ -43,6 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -59,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, SGMII_FM1_DTSEC4,
@@ -115,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -127,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
 	{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
 	{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -137,7 +158,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
 	{}
 };
 
@@ -150,6 +170,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 	{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE,  NONE,  SATA1, SATA2} },
 	{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
 	{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },

arch/powerpc/cpu/mpc85xx/t4240_serdes.c

@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, XFI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
 	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+	{5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+	{11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
 	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+	{13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
 	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
 	{}
@@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{}
 };
 static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		NONE, NONE} },
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{55, {NONE, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, NONE,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {NONE, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, NONE,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+	{11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
 	{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+	{13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
 	{}

arch/powerpc/include/asm/config_mpc85xx.h

@@ -38,6 +38,7 @@
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_MPC8540)
@@ -122,6 +123,7 @@
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_MPC8572)
@@ -132,6 +134,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1010)
@@ -154,6 +157,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
@@ -171,6 +175,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1012 is single core version of P1021 */
@@ -188,6 +193,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1013 is single core version of P1022 */
@@ -202,6 +208,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1014)
@@ -219,6 +226,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -234,6 +242,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1020)
@@ -246,6 +255,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
@@ -264,6 +274,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
@@ -278,6 +289,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1023)
@@ -293,6 +305,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
@@ -309,6 +322,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1025 is lower end variant of P1021 */
@@ -326,6 +340,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P2010 is single core version of P2020 */
@@ -338,6 +353,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P2020)
@@ -353,8 +369,10 @@
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -657,8 +675,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
@@ -684,12 +704,14 @@
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
@@ -809,8 +831,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 
 #elif defined(CONFIG_PPC_C29X)

arch/powerpc/include/asm/fsl_law.h

@@ -68,6 +68,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
 	LAW_TRGT_IF_BMAN = 0x18,
 	LAW_TRGT_IF_DCSR = 0x1d,
+	LAW_TRGT_IF_CCSR = 0x1e,
 	LAW_TRGT_IF_LBC = 0x1f,
 	LAW_TRGT_IF_QMAN = 0x3c,
 

arch/powerpc/include/asm/fsl_liodn.h

@@ -103,6 +103,10 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
 		CONFIG_SYS_MPC85xx_QE_OFFSET)
 
+#define SET_TDM_LIODN(liodn) \
+	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+		CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \

arch/powerpc/include/asm/immap_85xx.h

@@ -1899,7 +1899,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u32	sata2liodnr;	/* SATA 2 LIODN */
 	u32	sata3liodnr;	/* SATA 3 LIODN */
 	u32	sata4liodnr;	/* SATA 4 LIODN */
-	u8      res22[24];
+	u8	res22[20];
+	u32	tdmliodnr;	/* TDM LIODN */
 	u32     qeliodnr;       /* QE LIODN */
 	u8      res_57c[4];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
@@ -2521,14 +2522,17 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
 #define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_125	0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_0	0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072	0x000c0000
 #define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
 		u32	pllcr1; /* PLL Control Register 1 */
@@ -2863,6 +2867,21 @@ struct ccsr_pman {
 	u8	res_f4[0xf0c];
 };
 #endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+	u32 ospr;		/* 0x200 */
+	u32 reserved0[14];
+	u32 srk_hash[8];	/* 0x23c Super Root Key Hash */
+	u32 oem_uid;		/* 0x9c OEM Unique ID */
+	u8 reserved2[0x04];
+	u32 ovpr;			/* 0xA4  Intent To Secure */
+	u8 reserved4[0x08];
+	u32 fsl_uid;		/* 0xB0  FSL Unique ID */
+	u8 reserved5[0x04];
+	u32 fsl_spfr0;		/* Scratch Pad Fuse Register 0 */
+	u32 fsl_spfr1;		/* Scratch Pad Fuse Register 1 */
+};
+#endif
 
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
@@ -2876,6 +2895,14 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ *  * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET                  0x200
+#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
@@ -2889,6 +2916,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
@@ -3094,6 +3122,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_PCIE4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 
+#define CONFIG_SYS_SFP_ADDR  \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 

board/freescale/b4860qds/b4860qds.c

@@ -488,6 +488,9 @@ int configure_vsc3316_3308(void)
 	}
 
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0x98:
@@ -852,6 +855,9 @@ int config_serdes2_refclks(void)
 	 * For this SerDes2's Refclk1 need to be set to 100MHz
 	 */
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0xb2:

board/freescale/t208xqds/ddr.h

@@ -25,21 +25,21 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{2,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
-	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{2,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
-	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{2,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
-	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
-	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 

board/freescale/t208xqds/eth_t208xqds.c

@@ -416,6 +416,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 
 	switch (srds_s1) {
+	case 0x1b:
 	case 0x1c:
 	case 0x95:
 	case 0xa2:
@@ -429,8 +430,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x50:
 	case 0x51:
+	case 0x5e:
 	case 0x5f:
+	case 0x64:
 	case 0x65:
 		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
@@ -439,6 +443,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
 	case 0x66:
+	case 0x67:
 		/*
 		 * XFI does not need a PHY to work, but to avoid U-boot use
 		 * default PHY address which is zero to a MAC when it found
@@ -453,6 +458,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC3, 6);
 		fm_info_set_phy_address(FM1_10GEC4, 7);
 		break;
+	case 0x6a:
 	case 0x6b:
 		fm_info_set_phy_address(FM1_10GEC1, 4);
 		fm_info_set_phy_address(FM1_10GEC2, 5);
@@ -470,6 +476,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x70:
 	case 0x71:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
@@ -625,6 +632,7 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 
 			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 			    (srds_s1 == 0x71)) {
 				/* As XFI is in cage intead of a slot, so

board/freescale/t208xqds/t2080_rcw.cfg

@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/2133MT/s
 12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
+66150002 00008400 e8104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004

board/freescale/t208xqds/t208xqds.c

@@ -105,6 +105,7 @@ int brd_mux_lane_to_slot(void)
 		/* SerDes1 is not enabled */
 		break;
 #if defined(CONFIG_T2080QDS)
+	case 0x1b:
 	case 0x1c:
 	case 0xa2:
 		/* SD1(A:D) => SLOT3 SGMII
@@ -126,6 +127,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0x3a);
 		break;
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT3 XAUI
 		 * SD1(E)   => SLOT1 PCIe4
@@ -140,6 +142,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0xfe);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI cage
 		 * SD1(E)   => SLOT1 PCIe4
@@ -184,6 +187,7 @@ int brd_mux_lane_to_slot(void)
 		 QIXIS_WRITE(brdcfg[12], 0x1a);
 		 break;
 #elif defined(CONFIG_T2081QDS)
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT2 XAUI
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -192,6 +196,7 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[12], 0x98);
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI SFP Module
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -201,13 +206,6 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
 	case 0x6c:
-		/* SD1(A:B) => XFI SFP Module
-		 * SD1(C:D) => SLOT2 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xe8);
-		QIXIS_WRITE(brdcfg[13], 0x0);
-		break;
 	case 0x6d:
 		/* SD1(A:B) => XFI SFP Module
 		 * SD1(C:D) => SLOT2 SGMII

board/freescale/t208xrdb/t2080_rcw.cfg

@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/1600MT/s
 120c0017 15000000 00000000 00000000
-66160002 00008400 ec104000 c1000000
+66150002 00008400 ec104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004

board/freescale/t4qds/eth.c

@@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
@@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
+	case 37:
 	case 38:
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][3]);
 		}
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
@@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 		break;
+	case 6:
 	case 7:
+	case 12:
 	case 13:
 	case 14:
+	case 15:
 	case 16:
+	case 21:
 	case 22:
 	case 23:
+	case 24:
 	case 25:
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
@@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
+	case 37:
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
@@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);

board/freescale/t4qds/t4240qds.c

@@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void)
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	switch (srds_prtcl_s1) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot1 */
 		vsc3316_fsm1_tx[0][1] = 14;
 		vsc3316_fsm1_tx[6][1] = 0;
 		vsc3316_fsm1_rx[1][1] = 2;
 		vsc3316_fsm1_rx[6][1] = 13;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* swap first lane and third lane on slot2 */
 		vsc3316_fsm1_tx[2][1] = 8;
@@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void)
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 	switch (srds_prtcl_s2) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot3 */
 		vsc3316_fsm2_tx[2][1] = 11;
 		vsc3316_fsm2_tx[5][1] = 4;
 		vsc3316_fsm2_rx[2][1] = 9;
 		vsc3316_fsm2_rx[4][1] = 7;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		/* swap first lane and third lane on slot4 */
 		vsc3316_fsm2_tx[6][1] = 3;
@@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes3 is not enabled */
 		break;
+	case 1:
 	case 2:
 	case 9:
 	case 10:
@@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD3MX_SLOT5;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 17:
+	case 18:
 	case 19:
 	case 20:
 		/* SD3(4:7) => SLOT6(0:3) */
@@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes4 is not enabled */
 		break;
+	case 1:
 	case 2:
 		/* 10b, SD4(0:7) => SLOT7(0:7) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT7;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
 		/* x1b, SD4(4:7) => SLOT8(0:3) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT8;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 9:
 	case 10:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 18:
 		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */

board/freescale/t4qds/t4_rcw.cfg

@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  1_28_6_12
+#serdes protocol  1_27_5_11
 16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
 00000000 ee0000ee 00000000 000307fc
 00000000 00000000 00000000 00000028

board/freescale/t4rdb/eth.c

@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	if (srds_prtcl_s1 == 28) {
+	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
 		/* SGMII */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);

board/freescale/t4rdb/t4_rcw.cfg

@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  28_56_2_10
+#serdes protocol  27_56_1_9
 16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
 00000000 ee0000ee 00000000 000287fc
 00000000 50000000 00000000 00000028

drivers/ddr/fsl/ctrl_regs.c

@@ -2304,5 +2304,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	ddr->debug[2] = 0x00000400;
 	ddr->debug[4] = 0xff800000;
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+	if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
+		ddr->debug[2] |= 0x00000200;	/* set bit 22 */
+#endif
+
 	return check_fsl_memctl_config_regs(ddr);
 }

drivers/ddr/fsl/interactive.c

@@ -1579,7 +1579,7 @@ void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
 		printf("%-3d-%3d: ", 128, 255);
 
 		for (i = 128; i <= 255; i++)
-			printf("%02x", spd->mod_section.uc[i - 60]);
+			printf("%02x", spd->mod_section.uc[i - 128]);
 
 		break;
 	}

drivers/spi/fsl_espi.c

@@ -15,8 +15,10 @@
 
 struct fsl_spi_slave {
 	struct spi_slave slave;
+	ccsr_espi_t	*espi;
 	unsigned int	div16;
 	unsigned int	pm;
+	int		tx_timeout;
 	unsigned int	mode;
 	size_t		cmd_len;
 	u8		cmd_buf[16];
@@ -25,11 +27,17 @@ struct fsl_spi_slave {
 };
 
 #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+#define US_PER_SECOND		1000000UL
 
 #define ESPI_MAX_CS_NUM		4
+#define ESPI_FIFO_WIDTH_BIT	32
 
 #define ESPI_EV_RNE		(1 << 9)
 #define ESPI_EV_TNF		(1 << 8)
+#define ESPI_EV_DON		(1 << 14)
+#define ESPI_EV_TXE		(1 << 15)
+#define ESPI_EV_RFCNT_SHIFT	24
+#define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
 
 #define ESPI_MODE_EN		(1 << 31)	/* Enable interface */
 #define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
@@ -61,6 +69,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	struct fsl_spi_slave *fsl;
 	sys_info_t sysinfo;
 	unsigned long spibrg = 0;
+	unsigned long spi_freq = 0;
 	unsigned char pm = 0;
 
 	if (!spi_cs_is_valid(bus, cs))
@@ -70,6 +79,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!fsl)
 		return NULL;
 
+	fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
 	fsl->mode = mode;
 	fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
 
@@ -91,6 +101,15 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		pm--;
 	fsl->pm = pm;
 
+	if (fsl->div16)
+		spi_freq = spibrg / ((pm + 1) * 2 * 16);
+	else
+		spi_freq = spibrg / ((pm + 1) * 2);
+
+	/* set tx_timeout to 10 times of one espi FIFO entry go out */
+	fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+				* 10), spi_freq);
+
 	return &fsl->slave;
 }
 
@@ -108,7 +127,7 @@ void spi_init(void)
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+	ccsr_espi_t *espi = fsl->espi;
 	unsigned char pm = fsl->pm;
 	unsigned int cs = slave->cs;
 	unsigned int mode =  fsl->mode;
@@ -161,24 +180,86 @@ void spi_release_bus(struct spi_slave *slave)
 
 }
 
+static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
+{
+	ccsr_espi_t *espi = fsl->espi;
+	unsigned int tmpdout, event;
+	int tmp_tx_timeout;
+
+	if (dout)
+		tmpdout = *(u32 *)dout;
+	else
+		tmpdout = 0;
+
+	out_be32(&espi->tx, tmpdout);
+	out_be32(&espi->event, ESPI_EV_TNF);
+	debug("***spi_xfer:...%08x written\n", tmpdout);
+
+	tmp_tx_timeout = fsl->tx_timeout;
+	/* Wait for eSPI transmit to go out */
+	while (tmp_tx_timeout--) {
+		event = in_be32(&espi->event);
+		if (event & ESPI_EV_DON || event & ESPI_EV_TXE) {
+			out_be32(&espi->event, ESPI_EV_TXE);
+			break;
+		}
+		udelay(1);
+	}
+
+	if (tmp_tx_timeout < 0)
+		debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
+}
+
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
+{
+	ccsr_espi_t *espi = fsl->espi;
+	unsigned int tmpdin, rx_times;
+	unsigned char *buf, *p_cursor;
+
+	if (bytes <= 0)
+		return 0;
+
+	rx_times = DIV_ROUND_UP(bytes, 4);
+	buf = (unsigned char *)malloc(4 * rx_times);
+	if (!buf) {
+		debug("SF: Failed to malloc memory.\n");
+		return -1;
+	}
+	p_cursor = buf;
+	while (rx_times--) {
+		tmpdin = in_be32(&espi->rx);
+		debug("***spi_xfer:...%08x readed\n", tmpdin);
+		*(u32 *)p_cursor = tmpdin;
+		p_cursor += 4;
+	}
+
+	if (din)
+		memcpy(din, buf, bytes);
+
+	free(buf);
+	out_be32(&espi->event, ESPI_EV_RNE);
+
+	return bytes;
+}
+
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 		void *data_in, unsigned long flags)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+	ccsr_espi_t *espi = fsl->espi;
-	unsigned int tmpdout, tmpdin, event;
+	unsigned int event, rx_bytes;
 	const void *dout = NULL;
 	void *din = NULL;
 	int len = 0;
 	int num_blks, num_chunks, max_tran_len, tran_len;
 	int num_bytes;
-	unsigned char *ch;
 	unsigned char *buffer = NULL;
 	size_t buf_len;
 	u8 *cmd_buf = fsl->cmd_buf;
 	size_t cmd_len = fsl->cmd_len;
 	size_t data_len = bitlen / 8;
 	size_t rx_offset = 0;
+	int rf_cnt;
 
 	max_tran_len = fsl->max_transfer_length;
 	switch (flags) {
@@ -217,9 +298,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 		break;
 	}
 
-	debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n",
+	debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n",
-	      slave->bus, slave->cs, *(uint *) dout,
+	      *(uint *)data_out, data_out, *(uint *)data_in, data_in, len);
-	      dout, *(uint *) din, din, len);
 
 	num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
 	while (num_chunks--) {
@@ -235,41 +315,34 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
 		/* Clear all eSPI events */
 		out_be32(&espi->event , 0xffffffff);
 		/* handle data in 32-bit chunks */
-		while (num_blks--) {
+		while (num_blks) {
-
 			event = in_be32(&espi->event);
 			if (event & ESPI_EV_TNF) {
-				tmpdout = *(u32 *)dout;
+				fsl_espi_tx(fsl, dout);
-
 				/* Set up the next iteration */
 				if (len > 4) {
 					len -= 4;
 					dout += 4;
 				}
-
-				out_be32(&espi->tx, tmpdout);
-				out_be32(&espi->event, ESPI_EV_TNF);
-				debug("***spi_xfer:...%08x written\n", tmpdout);
 			}
 
-			/* Wait for eSPI transmit to get out */
-			udelay(80);
-
 			event = in_be32(&espi->event);
 			if (event & ESPI_EV_RNE) {
-				tmpdin = in_be32(&espi->rx);
+				rf_cnt = ((event & ESPI_EV_RFCNT_MASK)
-				if (num_blks == 0 && num_bytes != 0) {
+						>> ESPI_EV_RFCNT_SHIFT);
-					ch = (unsigned char *)&tmpdin;
+				if (rf_cnt >= 4)
-					while (num_bytes--)
+					rx_bytes = 4;
-						*(unsigned char *)din++ = *ch++;
+				else if (num_blks == 1 && rf_cnt == num_bytes)
-				} else {
+					rx_bytes = num_bytes;
-					*(u32 *) din = tmpdin;
+				else
-					din += 4;
+					continue;
+				if (fsl_espi_rx(fsl, din, rx_bytes)
+						== rx_bytes) {
+					num_blks--;
+					if (din)
+						din = (unsigned char *)din
+							+ rx_bytes;
 				}
-
-				out_be32(&espi->event, in_be32(&espi->event)
-						| ESPI_EV_RNE);
-				debug("***spi_xfer:...%08x readed\n", tmpdin);
 			}
 		}
 		if (data_in) {
@@ -295,7 +368,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
-	ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+	ccsr_espi_t *espi = fsl->espi;
 	unsigned int com = 0;
 	size_t data_len = fsl->data_len;
 
@@ -307,7 +380,8 @@ void spi_cs_activate(struct spi_slave *slave)
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+	struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+	ccsr_espi_t *espi = fsl->espi;
 
 	/* clear the RXCNT and TXCNT */
 	out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));

include/configs/T1040QDS.h

@@ -201,6 +201,12 @@ unsigned long get_board_ddr_clk(void);
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
+
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \

include/configs/T104xRDB.h

@@ -230,6 +230,12 @@
 				CSPR_MSEL_NOR | \
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
+
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \

include/configs/T208xQDS.h

@@ -227,8 +227,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR3
 #undef CONFIG_FSL_DDR_INTERACTIVE