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https://github.com/AsahiLinux/u-boot
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board/ti/am335x: add support for beaglebone NOR Cape
This patch adds support of NOR cape[1] for both Beaglebone (white) and Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC chip-select[0] and accesses as external memory-mapped device. This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device. As GPMC chip-select[0] can be shared by multiple capes so NOR profile is not enabled by default in boards.cfg. Following changes are required to enable NOR cape detection when building am335x_boneblack board profile. Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
pekon gupta
Tom Rini
parent
85eb0de214
commit
3df3bc1e1d
2 changed files with 48 additions and 60 deletions
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@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
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{-1},
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};
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#endif
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#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
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#elif defined(CONFIG_NOR)
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static struct module_pin_mux bone_norcape_pin_mux[] = {
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{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
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{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
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{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
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{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
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{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
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{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
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{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
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{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
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{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
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{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
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{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
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{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
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{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
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{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
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{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
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{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
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{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
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{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
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{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
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{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
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{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
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{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
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{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
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{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
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{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
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{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
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{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
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{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
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{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
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{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
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{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
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{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
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{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
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{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
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{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
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{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
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{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
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{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
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{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
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{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
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{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
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{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
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{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
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{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
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{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
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{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
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{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
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{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
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{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
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{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
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{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
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{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
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{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
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{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
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{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
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{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
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{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
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{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
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{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
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{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
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{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
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{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
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{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
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{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
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{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
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{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
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{-1},
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};
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#endif
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#if defined(CONFIG_NOR_BOOT)
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static struct module_pin_mux norboot_pin_mux[] = {
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{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
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{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
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{-1},
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};
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void enable_norboot_pin_mux(void)
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{
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configure_module_pin_mux(norboot_pin_mux);
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configure_module_pin_mux(bone_norcape_pin_mux);
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}
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#endif
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@ -349,7 +322,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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configure_module_pin_mux(mmc0_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
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#elif defined(CONFIG_NOR)
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configure_module_pin_mux(bone_norcape_pin_mux);
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#else
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configure_module_pin_mux(mmc1_pin_mux);
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@ -393,6 +366,8 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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configure_module_pin_mux(mmc0_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#elif defined(CONFIG_NOR)
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configure_module_pin_mux(bone_norcape_pin_mux);
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#else
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configure_module_pin_mux(mmc1_pin_mux);
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#endif
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@ -27,3 +27,16 @@ void flash_cmd_reset(flash_info_t *info)
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see also:
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http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
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Config Option
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CONFIG_SYS_MAX_FLASH_SECT: Number of sectors available on Flash device
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CONFIG_SYS_FLASH_CFI_WIDTH: Data-width of the flash device
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CONFIG_CMD_FLASH: Enables Flash command library
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CONFIG_FLASH_CFI_DRIVER: Enables CFI Flash driver
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CONFIG_FLASH_CFI_MTD: Enables MTD frame work for NOR Flash devices
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