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Convert CONFIG_SYS_BOOK3E_HV to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_BOOK3E_HV

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-25 11:02:43 -04:00
parent a457ebd786
commit 3dab405b45
49 changed files with 44 additions and 14 deletions
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4
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -1216,6 +1216,10 @@ config SYS_FSL_LBC_CLK_DIV
config ENABLE_36BIT_PHYS
bool "Enable 36bit physical address space support"
config SYS_BOOK3E_HV
bool "Category E.HV is supported"
depends on BOOKE
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx

1
configs/P2041RDB_NAND_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SDCARD_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SPIFLASH_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_NAND_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SDCARD_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SPIFLASH_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SDCARD_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SPIFLASH_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_NAND_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SDCARD_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SPIFLASH_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1024RDB_NAND_defconfig
View file

@ -13,6 +13,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1024RDB_SDCARD_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_SPIFLASH_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1042D4RDB_NAND_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1042D4RDB_SDCARD_defconfig
View file

@ -13,6 +13,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_SPIFLASH_defconfig
View file

@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080QDS_NAND_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD

1
configs/T2080QDS_SDCARD_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080QDS_SECURE_BOOT_defconfig
View file

@ -6,6 +6,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y

1
configs/T2080QDS_SPIFLASH_defconfig
View file

@ -22,6 +22,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080QDS_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080RDB_NAND_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD

1
configs/T2080RDB_SDCARD_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080RDB_SPIFLASH_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

4
configs/T2080RDB_defconfig
View file

@ -12,8 +12,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
<<<<<<< HEAD
=======
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -22,7 +21,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

1
configs/T2080RDB_revD_NAND_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y

1
configs/T2080RDB_revD_SDCARD_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD

1
configs/T2080RDB_revD_SPIFLASH_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD

1
configs/T2080RDB_revD_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======

1
configs/T4240RDB_SDCARD_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

4
configs/T4240RDB_defconfig
View file

@ -12,8 +12,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
<<<<<<< HEAD
=======
CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -22,7 +21,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

1
configs/kmcent2_defconfig
View file

@ -11,6 +11,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"

1
include/configs/P2041RDB.h
View file

@ -25,7 +25,6 @@
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc

1
include/configs/T102xRDB.h
View file

@ -14,7 +14,6 @@
#include <linux/stringify.h>
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

1
include/configs/T104xRDB.h
View file

@ -53,7 +53,6 @@
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc

1
include/configs/T208xQDS.h
View file

@ -21,7 +21,6 @@
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

1
include/configs/T208xRDB.h
View file

@ -16,7 +16,6 @@
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

1
include/configs/T4240RDB.h
View file

@ -34,7 +34,6 @@
#endif /* CONFIG_RAMBOOT_PBL */
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc

1
include/configs/corenet_ds.h
View file

@ -28,7 +28,6 @@
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc

1
include/configs/kmcent2.h
View file

@ -133,7 +133,6 @@
#define KM_I2C_DEBLOCK_SDA 21
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc