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ARM: pantheon: add mmc definition

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Signed-off-by: Lei Wen <leiwen@marvell.com>
This commit is contained in:
Lei Wen 2011-10-03 20:33:41 +00:00 committed by Albert ARIBAUD
parent 23365af099
commit 3d90a2adcb
5 changed files with 60 additions and 0 deletions
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11
arch/arm/cpu/arm926ejs/pantheon/cpu.c
View file

@ -42,6 +42,9 @@ int arch_cpu_init(void)
struct panthmpmu_registers *mpmu = struct panthmpmu_registers *mpmu =
(struct panthmpmu_registers*) PANTHEON_MPMU_BASE; (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
struct panthapmu_registers *apmu =
(struct panthapmu_registers *) PANTHEON_APMU_BASE;
/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
val = readl(&cpuregs->cpu_conf); val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID; val = val | SET_MRVL_ID;
@ -65,6 +68,14 @@ int arch_cpu_init(void)
writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
#endif #endif
#ifdef CONFIG_MV_SDHCI
/* Enable mmc clock */
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
&apmu->sd1);
writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
&apmu->sd3);
#endif
icache_enable(); icache_enable();
return 0; return 0;

18
arch/arm/include/asm/arch-pantheon/config.h
View file

@ -47,4 +47,22 @@
#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_SYS_I2C_SLAVE 0xfe
#endif #endif
/*
* MMC definition
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_CMD_FAT 1
#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC 1
#define CONFIG_SDHCI 1
#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
#define CONFIG_MMC_SDMA 1
#define CONFIG_MV_SDHCI 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_EFI_PARTITION 1
#define CONFIG_SYS_MMC_NUM 2
#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
#endif
#endif /* _PANTHEON_CONFIG_H */ #endif /* _PANTHEON_CONFIG_H */

12
arch/arm/include/asm/arch-pantheon/cpu.h
View file

@ -42,6 +42,17 @@ struct panthmpmu_registers {
u32 acgr; /*0x1024*/ u32 acgr; /*0x1024*/
}; };
/*
* Application Power Management (APMU) Registers
* Refer Register Datasheet 9.2
*/
struct panthapmu_registers {
u8 pad0[0x0054];
u32 sd1; /*0x0054*/
u8 pad1[0x00e0 - 0x054 - 4];
u32 sd3; /*0x00e0*/
};
/* /*
* APB Clock Reset/Control Registers * APB Clock Reset/Control Registers
* Refer Register Datasheet 6.14 * Refer Register Datasheet 6.14
@ -77,5 +88,6 @@ struct panthcpu_registers {
*/ */
u32 panth_sdram_base(int); u32 panth_sdram_base(int);
u32 panth_sdram_size(int); u32 panth_sdram_size(int);
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
#endif /* _PANTHEON_CPU_H */ #endif /* _PANTHEON_CPU_H */

12
arch/arm/include/asm/arch-pantheon/mfp.h
View file

@ -38,6 +38,18 @@
#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) #define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* More macros can be defined here... */ /* More macros can be defined here... */
#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP_PIN_MAX 117 #define MFP_PIN_MAX 117
#endif #endif

7
arch/arm/include/asm/arch-pantheon/pantheon.h
View file

@ -32,6 +32,12 @@
/* Functional Clock Selection Mask */ /* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
/* Common APMU register bit definitions */
#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
#define APMU_AXI_RST (1<<0) /* AXI Reset */
/* Register Base Addresses */ /* Register Base Addresses */
#define PANTHEON_DRAM_BASE 0xB0000000 #define PANTHEON_DRAM_BASE 0xB0000000
#define PANTHEON_TIMER_BASE 0xD4014000 #define PANTHEON_TIMER_BASE 0xD4014000
@ -42,6 +48,7 @@
#define PANTHEON_GPIO_BASE 0xD4019000 #define PANTHEON_GPIO_BASE 0xD4019000
#define PANTHEON_MFPR_BASE 0xD401E000 #define PANTHEON_MFPR_BASE 0xD401E000
#define PANTHEON_MPMU_BASE 0xD4050000 #define PANTHEON_MPMU_BASE 0xD4050000
#define PANTHEON_APMU_BASE 0xD4282800
#define PANTHEON_CPU_BASE 0xD4282C00 #define PANTHEON_CPU_BASE 0xD4282C00
#endif /* _PANTHEON_H */ #endif /* _PANTHEON_H */