mirror of
https://github.com/AsahiLinux/u-boot
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arm: dts: Add dts and dtsi for Arria 10
Device tree files for Arria 10 Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
35b9800ff2
commit
3d5f7c5af3
4 changed files with 1389 additions and 0 deletions
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@ -149,6 +149,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
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dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_arria10_socdk_sdmmc.dtb \
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socfpga_arria5_socdk.dtb \
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socfpga_cyclone5_is1.dtb \
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socfpga_cyclone5_mcvevk.dtb \
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869
arch/arm/dts/socfpga_arria10.dtsi
Normal file
869
arch/arm/dts/socfpga_arria10.dtsi
Normal file
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@ -0,0 +1,869 @@
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/*
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* Copyright Altera Corporation (C) 2014-2017. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/altr,rst-mgr-a10.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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serial0 = &uart0;
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serial1 = &uart1;
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timer0 = &timer0;
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timer1 = &timer1;
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timer2 = &timer2;
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timer3 = &timer3;
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spi0 = &spi0;
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spi1 = &spi1;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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intc: intc@ffffd000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xffffd000 0x1000>,
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<0xffffc100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@ffda1000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffda1000 0x1000>;
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
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<0 84 IRQ_TYPE_LEVEL_HIGH>,
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<0 85 IRQ_TYPE_LEVEL_HIGH>,
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<0 86 IRQ_TYPE_LEVEL_HIGH>,
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<0 87 IRQ_TYPE_LEVEL_HIGH>,
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<0 88 IRQ_TYPE_LEVEL_HIGH>,
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<0 89 IRQ_TYPE_LEVEL_HIGH>,
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<0 90 IRQ_TYPE_LEVEL_HIGH>,
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<0 91 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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clocks = <&l4_main_clk>;
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clock-names = "apb_pclk";
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};
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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reg-names = "soc_clock_manager_OCP_SLV";
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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cb_intosc_ls_clk: cb_intosc_ls_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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f2s_free_clk: f2s_free_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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main_pll: main_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>;
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reg = <0x40>;
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main_mpu_base_clk: main_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x140 0 11>;
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};
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main_noc_base_clk: main_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x144 0 11>;
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};
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main_emaca_clk: main_emaca_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x68>;
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};
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main_emacb_clk: main_emacb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x6C>;
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};
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main_emac_ptp_clk: main_emac_ptp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x70>;
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};
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main_gpio_db_clk: main_gpio_db_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x74>;
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};
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main_sdmmc_clk: main_sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x78>;
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};
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main_s2f_usr0_clk: main_s2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x7C>;
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};
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main_s2f_usr1_clk: main_s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x80>;
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};
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main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x84>;
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};
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main_periph_ref_clk: main_periph_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x9C>;
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};
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};
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periph_pll: periph_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>, <&main_periph_ref_clk>;
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reg = <0xC0>;
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peri_mpu_base_clk: peri_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x140 16 11>;
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};
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peri_noc_base_clk: peri_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x144 16 11>;
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};
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peri_emaca_clk: peri_emaca_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xE8>;
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};
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peri_emacb_clk: peri_emacb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xEC>;
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};
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peri_emac_ptp_clk: peri_emac_ptp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF0>;
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};
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peri_gpio_db_clk: peri_gpio_db_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF4>;
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};
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peri_sdmmc_clk: peri_sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF8>;
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};
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peri_s2f_usr0_clk: peri_s2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xFC>;
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};
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peri_s2f_usr1_clk: peri_s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x100>;
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};
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peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x104>;
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};
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};
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mpu_free_clk: mpu_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x60>;
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};
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noc_free_clk: noc_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x64>;
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};
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s2f_user1_free_clk: s2f_user1_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x104>;
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};
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sdmmc_free_clk: sdmmc_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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fixed-divider = <4>;
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reg = <0xF8>;
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};
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l4_sys_free_clk: l4_sys_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&noc_free_clk>;
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fixed-divider = <4>;
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};
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l4_main_clk: l4_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 0 2>;
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clk-gate = <0x48 1>;
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};
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l4_mp_clk: l4_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 8 2>;
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clk-gate = <0x48 2>;
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};
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l4_sp_clk: l4_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 16 2>;
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clk-gate = <0x48 3>;
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};
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mpu_periph_clk: mpu_periph_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&mpu_free_clk>;
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fixed-divider = <4>;
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clk-gate = <0x48 0>;
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};
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sdmmc_clk: sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&sdmmc_free_clk>;
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clk-gate = <0xC8 5>;
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clk-phase = <0 135>;
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};
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qspi_clk: qspi_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 11>;
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};
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nand_clk: nand_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 10>;
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};
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 9>;
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};
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usb_clk: usb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 8>;
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};
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s2f_usr1_clk: s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&peri_s2f_usr1_clk>;
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clk-gate = <0xC8 6>;
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};
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};
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x44 0>;
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reg = <0xff800000 0x2000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <16384>;
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clocks = <&l4_mp_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC0_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
|
||||
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
|
||||
reg = <0xff802000 0x2000>;
|
||||
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
/* Filled in by bootloader */
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
tx-fifo-depth = <4096>;
|
||||
rx-fifo-depth = <16384>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&rst EMAC1_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac2: ethernet@ff804000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
|
||||
altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
|
||||
reg = <0xff804000 0x2000>;
|
||||
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
/* Filled in by bootloader */
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
tx-fifo-depth = <4096>;
|
||||
rx-fifo-depth = <16384>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@ffc02900 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xffc02900 0x100>;
|
||||
status = "disabled";
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <29>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@ffc02a00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xffc02a00 0x100>;
|
||||
status = "disabled";
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <29>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@ffc02b00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xffc02b00 0x100>;
|
||||
status = "disabled";
|
||||
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <27>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga_mgr: fpga-mgr@ffd03000 {
|
||||
compatible = "altr,socfpga-a10-fpga-mgr";
|
||||
reg = <0xffd03000 0x100
|
||||
0xffcfe400 0x20>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
resets = <&rst FPGAMGR_RESET>;
|
||||
reset-names = "fpgamgr";
|
||||
};
|
||||
|
||||
i2c0: i2c@ffc02200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc02200 0x100>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@ffc02300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc02300 0x100>;
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@ffc02400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc02400 0x100>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@ffc02500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc02500 0x100>;
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@ffc02600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc02600 0x100>;
|
||||
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdr: sdr@0xffcfb100 {
|
||||
compatible = "syscon";
|
||||
reg = <0xffcfb100 0x80>;
|
||||
};
|
||||
|
||||
spi0: spi@ffda4000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xffda4000 0x100>;
|
||||
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-chipselect = <4>;
|
||||
bus-num = <0>;
|
||||
tx-dma-channel = <&pdma 16>;
|
||||
rx-dma-channel = <&pdma 17>;
|
||||
clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@ffda5000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xffda5000 0x100>;
|
||||
interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-chipselect = <4>;
|
||||
bus-num = <0>;
|
||||
tx-dma-channel = <&pdma 20>;
|
||||
rx-dma-channel = <&pdma 21>;
|
||||
clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
L2: l2-cache@fffff000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfffff000 0x1000>;
|
||||
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
mmc: dwmmc0@ff808000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "altr,socfpga-dw-mshc";
|
||||
reg = <0xff808000 0x1000>;
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fifo-depth = <0x400>;
|
||||
bus-width = <4>;
|
||||
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
|
||||
clock-names = "biu", "ciu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ocram: sram@ffe00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffe00000 0x40000>;
|
||||
};
|
||||
|
||||
eccmgr: eccmgr@ffd06000 {
|
||||
compatible = "altr,socfpga-a10-ecc-manager";
|
||||
altr,sysmgr-syscon = <&sysmgr>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac-a10";
|
||||
altr,sdr-syscon = <&sdr>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
l2-ecc@ffd06010 {
|
||||
compatible = "altr,socfpga-a10-l2-ecc";
|
||||
reg = <0xffd06010 0x4>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocram-ecc@ff8c3000 {
|
||||
compatible = "altr,socfpga-a10-ocram-ecc";
|
||||
reg = <0xff8c3000 0x400>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmca-ecc@ff8c2c00 {
|
||||
compatible = "altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c2c00 0x400>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-rx-ecc@ff8c0800 {
|
||||
compatible = "altr,socfpga-eth-mac-ecc";
|
||||
reg = <0xff8c0800 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-tx-ecc@ff8c0c00 {
|
||||
compatible = "altr,socfpga-eth-mac-ecc";
|
||||
reg = <0xff8c0c00 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-dma-ecc";
|
||||
reg = <0xff8c8000 0x400>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usb0-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-usb-ecc";
|
||||
reg = <0xff8c8800 0x400>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi: qspi@ff809000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "cadence,qspi";
|
||||
reg = <0xff809000 0x100>,
|
||||
<0xffa00000 0x100000>;
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_main_clk>;
|
||||
ext-decoder = <0>; /* external decoder */
|
||||
num-chipselect = <4>;
|
||||
fifo-depth = <128>;
|
||||
sram-size = <512>;
|
||||
bus-num = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rst: rstmgr@ffd05000 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x100>;
|
||||
altr,modrst-offset = <0x20>;
|
||||
};
|
||||
|
||||
scu: snoop-control-unit@ffffc000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xffffc000 0x100>;
|
||||
};
|
||||
|
||||
sysmgr: sysmgr@ffd06000 {
|
||||
compatible = "altr,sys-mgr", "syscon";
|
||||
reg = <0xffd06000 0x300>;
|
||||
cpu1-start-addr = <0xffd06230>;
|
||||
};
|
||||
|
||||
/* Local timer */
|
||||
timer@ffffc600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xffffc600 0x100>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
clocks = <&mpu_periph_clk>;
|
||||
};
|
||||
|
||||
timer0: timer0@ffc02700 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xffc02700 0x100>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
timer1: timer1@ffc02800 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xffc02800 0x100>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
timer2: timer2@ffd00000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xffd00000 0x100>;
|
||||
clocks = <&l4_sys_free_clk>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
timer3: timer3@ffd00100 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xffd01000 0x100>;
|
||||
clocks = <&l4_sys_free_clk>;
|
||||
clock-names = "timer";
|
||||
};
|
||||
|
||||
uart0: serial0@ffc02000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02000 0x100>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial1@ffc02100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02100 0x100>;
|
||||
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb0: usb@ffb00000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0xffb00000 0xffff>;
|
||||
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_clk>;
|
||||
clock-names = "otg";
|
||||
resets = <&rst USB0_RESET>;
|
||||
reset-names = "dwc2";
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@ffb40000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0xffb40000 0xffff>;
|
||||
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_clk>;
|
||||
clock-names = "otg";
|
||||
resets = <&rst USB1_RESET>;
|
||||
reset-names = "dwc2";
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@ffd00200 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00200 0x100>;
|
||||
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sys_free_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog1: watchdog@ffd00300 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00300 0x100>;
|
||||
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l4_sys_free_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
38
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
Normal file
38
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Altera Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
cap-sd-highspeed;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
};
|
||||
481
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
Normal file
481
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
Normal file
|
|
@ -0,0 +1,481 @@
|
|||
/*
|
||||
* Copyright (C) 2016-2017 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0 X11
|
||||
*
|
||||
*<auto-generated>
|
||||
* This code was generated by a tool based on
|
||||
* handoffs from both Qsys and Quartus.
|
||||
*
|
||||
* Changes to this file may be lost if
|
||||
* the code is regenerated.
|
||||
*</auto-generated>
|
||||
*/
|
||||
|
||||
#include "socfpga_arria10.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Arria 10";
|
||||
compatible = "altr,socfpga-arria10", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
/* Bootloader setting: uboot.rbf_filename */
|
||||
cff-file = "ghrd_10as066n2.periph.rbf";
|
||||
early-release-fpga-config;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
clkmgr@ffd04000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
clocks {
|
||||
u-boot,dm-pre-reloc;
|
||||
osc1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "altera_arria10_hps_eosc1-clk";
|
||||
};
|
||||
|
||||
cb_intosc_ls_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
clock-frequency = <60000000>;
|
||||
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
|
||||
};
|
||||
|
||||
f2s_free_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "altera_arria10_hps_f2h_free-clk";
|
||||
};
|
||||
|
||||
main_pll {
|
||||
u-boot,dm-pre-reloc;
|
||||
/*
|
||||
* Address Block: soc_clock_manager_OCP_SLV.
|
||||
* i_clk_mgr_mainpllgrp
|
||||
*/
|
||||
altr,of_reg_value = <
|
||||
0 /* Field: vco0.psrc */
|
||||
1 /* Field: vco1.denom */
|
||||
191 /* Field: vco1.numer */
|
||||
0 /* Field: mpuclk */
|
||||
0 /* Field: mpuclk.cnt */
|
||||
0 /* Field: mpuclk.src */
|
||||
0 /* Field: nocclk */
|
||||
0 /* Field: nocclk.cnt */
|
||||
0 /* Field: nocclk.src */
|
||||
900 /* Field: cntr2clk.cnt */
|
||||
900 /* Field: cntr3clk.cnt */
|
||||
900 /* Field: cntr4clk.cnt */
|
||||
900 /* Field: cntr5clk.cnt */
|
||||
900 /* Field: cntr6clk.cnt */
|
||||
900 /* Field: cntr7clk.cnt */
|
||||
0 /* Field: cntr7clk.src */
|
||||
900 /* Field: cntr8clk.cnt */
|
||||
900 /* Field: cntr9clk.cnt */
|
||||
0 /* Field: cntr9clk.src */
|
||||
900 /* Field: cntr15clk.cnt */
|
||||
0 /* Field: nocdiv.l4mainclk */
|
||||
0 /* Field: nocdiv.l4mpclk */
|
||||
2 /* Field: nocdiv.l4spclk */
|
||||
0 /* Field: nocdiv.csatclk */
|
||||
1 /* Field: nocdiv.cstraceclk */
|
||||
1 /* Field: nocdiv.cspdbgclk */
|
||||
>;
|
||||
};
|
||||
|
||||
periph_pll {
|
||||
u-boot,dm-pre-reloc;
|
||||
/*
|
||||
* Address Block: soc_clock_manager_OCP_SLV.
|
||||
* i_clk_mgr_perpllgrp
|
||||
*/
|
||||
altr,of_reg_value = <
|
||||
0 /* Field: vco0.psrc */
|
||||
1 /* Field: vco1.denom */
|
||||
159 /* Field: vco1.numer */
|
||||
7 /* Field: cntr2clk.cnt */
|
||||
1 /* Field: cntr2clk.src */
|
||||
900 /* Field: cntr3clk.cnt */
|
||||
1 /* Field: cntr3clk.src */
|
||||
19 /* Field: cntr4clk.cnt */
|
||||
1 /* Field: cntr4clk.src */
|
||||
499 /* Field: cntr5clk.cnt */
|
||||
1 /* Field: cntr5clk.src */
|
||||
9 /* Field: cntr6clk.cnt */
|
||||
1 /* Field: cntr6clk.src */
|
||||
900 /* Field: cntr7clk.cnt */
|
||||
900 /* Field: cntr8clk.cnt */
|
||||
0 /* Field: cntr8clk.src */
|
||||
900 /* Field: cntr9clk.cnt */
|
||||
0 /* Field: emacctl.emac0sel */
|
||||
0 /* Field: emacctl.emac1sel */
|
||||
0 /* Field: emacctl.emac2sel */
|
||||
32000 /* Field: gpiodiv.gpiodbclk */
|
||||
>;
|
||||
};
|
||||
|
||||
altera {
|
||||
u-boot,dm-pre-reloc;
|
||||
/*
|
||||
* Address Block: soc_clock_manager_OCP_SLV.
|
||||
* i_clk_mgr_alteragrp
|
||||
*/
|
||||
altr,of_reg_value = <
|
||||
0x0384000b /* Register: nocclk */
|
||||
0x03840001 /* Register: mpuclk */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
|
||||
* Binding: pinmux
|
||||
*/
|
||||
i_io48_pin_mux: pinmux@0xffd07000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0xffd07000 0x00000800>;
|
||||
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
|
||||
|
||||
/*
|
||||
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
||||
* i_io48_pin_mux_shared_3v_io_grp
|
||||
*/
|
||||
shared {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0xffd07000 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
/* Reg: pinmux_shared_io_q1_1 */
|
||||
<0x00000000 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_2 */
|
||||
<0x00000004 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_3 */
|
||||
<0x00000008 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_4 */
|
||||
<0x0000000c 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_5 */
|
||||
<0x00000010 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_6 */
|
||||
<0x00000014 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_7 */
|
||||
<0x00000018 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_8 */
|
||||
<0x0000001c 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_9 */
|
||||
<0x00000020 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_10 */
|
||||
<0x00000024 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_11 */
|
||||
<0x00000028 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q1_12 */
|
||||
<0x0000002c 0x00000008>,
|
||||
/* Reg: pinmux_shared_io_q2_1 */
|
||||
<0x00000030 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_2 */
|
||||
<0x00000034 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_3 */
|
||||
<0x00000038 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_4 */
|
||||
<0x0000003c 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_5 */
|
||||
<0x00000040 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_6 */
|
||||
<0x00000044 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_7 */
|
||||
<0x00000048 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_8 */
|
||||
<0x0000004c 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_9 */
|
||||
<0x00000050 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_10 */
|
||||
<0x00000054 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_11 */
|
||||
<0x00000058 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q2_12 */
|
||||
<0x0000005c 0x00000004>,
|
||||
/* Reg: pinmux_shared_io_q3_1 */
|
||||
<0x00000060 0x00000003>,
|
||||
/* Reg: pinmux_shared_io_q3_2 */
|
||||
<0x00000064 0x00000003>,
|
||||
/* Reg: pinmux_shared_io_q3_3 */
|
||||
<0x00000068 0x00000003>,
|
||||
/* Reg: pinmux_shared_io_q3_4 */
|
||||
<0x0000006c 0x00000003>,
|
||||
/* Reg: pinmux_shared_io_q3_5 */
|
||||
<0x00000070 0x00000003>,
|
||||
/* Reg: pinmux_shared_io_q3_6 */
|
||||
<0x00000074 0x0000000f>,
|
||||
/* Reg: pinmux_shared_io_q3_7 */
|
||||
<0x00000078 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q3_8 */
|
||||
<0x0000007c 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q3_9 */
|
||||
<0x00000080 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q3_10 */
|
||||
<0x00000084 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q3_11 */
|
||||
<0x00000088 0x00000001>,
|
||||
/* Reg: pinmux_shared_io_q3_12 */
|
||||
<0x0000008c 0x00000001>,
|
||||
/* Reg: pinmux_shared_io_q4_1 */
|
||||
<0x00000090 0x00000000>,
|
||||
/* Reg: pinmux_shared_io_q4_2 */
|
||||
<0x00000094 0x00000000>,
|
||||
/* Reg: pinmux_shared_io_q4_3 */
|
||||
<0x00000098 0x0000000f>,
|
||||
/* Reg: pinmux_shared_io_q4_4 */
|
||||
<0x0000009c 0x0000000c>,
|
||||
/* Reg: pinmux_shared_io_q4_5 */
|
||||
<0x000000a0 0x0000000f>,
|
||||
/* Reg: pinmux_shared_io_q4_6 */
|
||||
<0x000000a4 0x0000000f>,
|
||||
/* Reg: pinmux_shared_io_q4_7 */
|
||||
<0x000000a8 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q4_8 */
|
||||
<0x000000ac 0x0000000a>,
|
||||
/* Reg: pinmux_shared_io_q4_9 */
|
||||
<0x000000b0 0x0000000c>,
|
||||
/* Reg: pinmux_shared_io_q4_10 */
|
||||
<0x000000b4 0x0000000c>,
|
||||
/* Reg: pinmux_shared_io_q4_11 */
|
||||
<0x000000b8 0x0000000c>,
|
||||
/* Reg: pinmux_shared_io_q4_12 */
|
||||
<0x000000bc 0x0000000c>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
||||
* i_io48_pin_mux_dedicated_io_grp
|
||||
*/
|
||||
dedicated {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
/* Reg: pinmux_dedicated_io_4 */
|
||||
<0x0000000c 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_5 */
|
||||
<0x00000010 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_6 */
|
||||
<0x00000014 0x00000008>,
|
||||
/* Regi: pinmux_dedicated_io_7 */
|
||||
<0x00000018 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_8 */
|
||||
<0x0000001c 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_9 */
|
||||
<0x00000020 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_10 */
|
||||
<0x00000024 0x0000000a>,
|
||||
/* Reg: pinmux_dedicated_io_11 */
|
||||
<0x00000028 0x0000000a>,
|
||||
/* Reg: pinmux_dedicated_io_12 */
|
||||
<0x0000002c 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_13 */
|
||||
<0x00000030 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_14 */
|
||||
<0x00000034 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_15 */
|
||||
<0x00000038 0x00000008>,
|
||||
/* Reg: pinmux_dedicated_io_16 */
|
||||
<0x0000003c 0x0000000d>,
|
||||
/* Reg: pinmux_dedicated_io_17 */
|
||||
<0x00000040 0x0000000d>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
||||
* i_io48_pin_mux_dedicated_io_grp
|
||||
*/
|
||||
dedicated_cfg {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x003f3f3f>;
|
||||
pinctrl-single,pins =
|
||||
/* Reg: cfg_dedicated_io_bank */
|
||||
<0x00000100 0x00000101>,
|
||||
/* Reg: cfg_dedicated_io_1 */
|
||||
<0x00000104 0x000b080a>,
|
||||
/* Reg: cfg_dedicated_io_2 */
|
||||
<0x00000108 0x000b080a>,
|
||||
/* Reg: cfg_dedicated_io_3 */
|
||||
<0x0000010c 0x000b080a>,
|
||||
/* Reg: cfg_dedicated_io_4 */
|
||||
<0x00000110 0x000a282a>,
|
||||
/* Reg: cfg_dedicated_io_5 */
|
||||
<0x00000114 0x000a282a>,
|
||||
/* Reg: cfg_dedicated_io_6 */
|
||||
<0x00000118 0x0008282a>,
|
||||
/* Reg: cfg_dedicated_io_7 */
|
||||
<0x0000011c 0x000a282a>,
|
||||
/* Reg: cfg_dedicated_io_8 */
|
||||
<0x00000120 0x000a282a>,
|
||||
/* Reg: cfg_dedicated_io_9 */
|
||||
<0x00000124 0x000a282a>,
|
||||
/* Reg: cfg_dedicated_io_10 */
|
||||
<0x00000128 0x00090000>,
|
||||
/* Reg: cfg_dedicated_io_11 */
|
||||
<0x0000012c 0x00090000>,
|
||||
/* Reg: cfg_dedicated_io_12 */
|
||||
<0x00000130 0x000b282a>,
|
||||
/* Reg: cfg_dedicated_io_13 */
|
||||
<0x00000134 0x000b282a>,
|
||||
/* Reg: cfg_dedicated_io_14 */
|
||||
<0x00000138 0x000b282a>,
|
||||
/* Reg: cfg_dedicated_io_15 */
|
||||
<0x0000013c 0x000b282a>,
|
||||
/* Reg: cfg_dedicated_io_16 */
|
||||
<0x00000140 0x0008282a>,
|
||||
/* Reg: cfg_dedicated_io_17 */
|
||||
<0x00000144 0x000a282a>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
||||
* i_io48_pin_mux_fpga_interface_grp
|
||||
*/
|
||||
fpga {
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0xffd07400 0x00000100>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x00000001>;
|
||||
pinctrl-single,pins =
|
||||
/* Reg: pinmux_emac0_usefpga */
|
||||
<0x00000000 0x00000000>,
|
||||
/* Reg: pinmux_emac1_usefpga */
|
||||
<0x00000004 0x00000000>,
|
||||
/* Reg: pinmux_emac2_usefpga */
|
||||
<0x00000008 0x00000000>,
|
||||
/* Reg: pinmux_i2c0_usefpga */
|
||||
<0x0000000c 0x00000000>,
|
||||
/* Reg: pinmux_i2c1_usefpga */
|
||||
<0x00000010 0x00000000>,
|
||||
/* Reg: pinmux_i2c_emac0_usefpga */
|
||||
<0x00000014 0x00000000>,
|
||||
/* Reg: pinmux_i2c_emac1_usefpga */
|
||||
<0x00000018 0x00000000>,
|
||||
/* Reg: pinmux_i2c_emac2_usefpga */
|
||||
<0x0000001c 0x00000000>,
|
||||
/* Reg: pinmux_nand_usefpga */
|
||||
<0x00000020 0x00000000>,
|
||||
/* Reg: pinmux_qspi_usefpga */
|
||||
<0x00000024 0x00000000>,
|
||||
/* Reg: pinmux_sdmmc_usefpga */
|
||||
<0x00000028 0x00000000>,
|
||||
/* Reg: pinmux_spim0_usefpga */
|
||||
<0x0000002c 0x00000000>,
|
||||
/* Reg: pinmux_spim1_usefpga */
|
||||
<0x00000030 0x00000000>,
|
||||
/* Reg: pinmux_spis0_usefpga */
|
||||
<0x00000034 0x00000000>,
|
||||
/* Reg: pinmux_spis1_usefpga */
|
||||
<0x00000038 0x00000000>,
|
||||
/* Reg: pinmux_uart0_usefpga */
|
||||
<0x0000003c 0x00000000>,
|
||||
/* Reg: pinmux_uart1_usefpga */
|
||||
<0x00000040 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i_noc: noc@0xffd10000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "altr,socfpga-a10-noc";
|
||||
reg = <0xffd10000 0x00008000>;
|
||||
reg-names = "mpu_m0";
|
||||
|
||||
firewall {
|
||||
u-boot,dm-pre-reloc;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* mpuregion0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* mpuregion0addr.limit
|
||||
*/
|
||||
altr,mpu0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
||||
* hpsregion0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
||||
* hpsregion0addr.limit
|
||||
*/
|
||||
altr,l3-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram0region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram0region0addr.limit
|
||||
*/
|
||||
altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram1region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram1region0addr.limit
|
||||
*/
|
||||
altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram2region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
||||
* I_NOC.mpu_m0.
|
||||
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
||||
* fpga2sdram2region0addr.limit
|
||||
*/
|
||||
altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
|
||||
};
|
||||
};
|
||||
|
||||
hps_fpgabridge0: fpgabridge@0 {
|
||||
compatible = "altr,socfpga-hps2fpga-bridge";
|
||||
altr,init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge1: fpgabridge@1 {
|
||||
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||||
altr,init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge2: fpgabridge@2 {
|
||||
compatible = "altr,socfpga-fpga2hps-bridge";
|
||||
altr,init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge3: fpgabridge@3 {
|
||||
compatible = "altr,socfpga-fpga2sdram0-bridge";
|
||||
altr,init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge4: fpgabridge@4 {
|
||||
compatible = "altr,socfpga-fpga2sdram1-bridge";
|
||||
altr,init-val = <0>;
|
||||
};
|
||||
|
||||
hps_fpgabridge5: fpgabridge@5 {
|
||||
compatible = "altr,socfpga-fpga2sdram2-bridge";
|
||||
altr,init-val = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue