mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 17:41:08 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-nds32
* 'master' of git://git.denx.de/u-boot-nds32: nds32: split common cache access from cpu into lib Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
commit
3c692f9706
4 changed files with 158 additions and 225 deletions
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@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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/*NOTREACHED*/
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}
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
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{
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if (cache == ICACHE)
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1);
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else
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1);
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}
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void dcache_flush_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
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start += line_size;
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}
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}
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void icache_inval_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
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start += line_size;
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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dcache_flush_range(addr, addr + size);
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icache_inval_range(addr, addr + size);
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}
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void icache_enable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x01\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void icache_disable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x01\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int icache_status(void)
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{
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int ret;
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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void dcache_enable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x02\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void dcache_disable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x02\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int dcache_status(void)
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{
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int ret;
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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/*NOTREACHED*/
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}
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
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{
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if (cache == ICACHE)
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1);
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else
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1);
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}
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void dcache_flush_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
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start += line_size;
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}
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}
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void icache_inval_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
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start += line_size;
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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dcache_flush_range(addr, addr + size);
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icache_inval_range(addr, addr + size);
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}
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void icache_enable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x01\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void icache_disable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x01\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int icache_status(void)
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{
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int ret;
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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void dcache_enable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x02\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void dcache_disable(void)
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{
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x02\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int dcache_status(void)
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{
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int ret;
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__asm__ __volatile__ (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(ARCH).o
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OBJS := board.o bootm.o interrupts.o
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OBJS := board.o bootm.o cache.o interrupts.o
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all: $(LIB)
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157
arch/nds32/lib/cache.c
Normal file
157
arch/nds32/lib/cache.c
Normal file
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@ -0,0 +1,157 @@
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/*
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* Copyright (C) 2012 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
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{
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if (cache == ICACHE)
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1);
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else
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1);
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_WB"
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"\n\tcctl %0, L1D_VA_INVAL"
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:
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: "r" (start)
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);
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start += line_size;
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}
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1I_VA_INVAL"
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:
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: "r"(start)
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);
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start += line_size;
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}
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_INVAL"
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:
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: "r"(start)
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);
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start += line_size;
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr, addr + size);
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invalidate_icache_range(addr, addr + size);
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}
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void icache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x01\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void icache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x01\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int icache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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void dcache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x02\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void dcache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x02\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int dcache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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