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https://github.com/AsahiLinux/u-boot
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powerpc: MPC8555: Remove macro CONFIG_MPC8555
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
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4096f350d5
commit
3c3d8ab58d
13 changed files with 15 additions and 13 deletions
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@ -76,6 +76,7 @@ config TARGET_MPC8548CDS
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config TARGET_MPC8555CDS
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config TARGET_MPC8555CDS
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bool "Support MPC8555CDS"
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bool "Support MPC8555CDS"
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select ARCH_MPC8555
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config TARGET_MPC8560ADS
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config TARGET_MPC8560ADS
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bool "Support MPC8560ADS"
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bool "Support MPC8560ADS"
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@ -207,6 +208,9 @@ config ARCH_MPC8544
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config ARCH_MPC8548
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config ARCH_MPC8548
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bool
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bool
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config ARCH_MPC8555
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bool
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -294,7 +294,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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{
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/* Everything after the first generation of PQ3 parts has RSTCR */
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/* Everything after the first generation of PQ3 parts has RSTCR */
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
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defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_MPC8560)
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unsigned long val, msr;
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unsigned long val, msr;
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/*
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/*
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@ -626,7 +626,7 @@ void get_sys_info(sys_info_t *sys_info)
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*/
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*/
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lcrr_div *= 4;
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lcrr_div *= 4;
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#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
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#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
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!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
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!defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560)
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/*
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/*
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* Yes, the entire PQ38 family use the same
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider values.
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* bit-representation for twice the clock divider values.
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@ -682,7 +682,7 @@ int get_clocks (void)
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* AN2919.
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* AN2919.
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*/
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*/
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
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defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
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defined(CONFIG_P1022)
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defined(CONFIG_P1022)
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gd->arch.i2c1_clk = sys_info.freq_systembus;
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gd->arch.i2c1_clk = sys_info.freq_systembus;
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#elif defined(CONFIG_ARCH_MPC8544)
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#elif defined(CONFIG_ARCH_MPC8544)
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@ -85,7 +85,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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#elif defined(CONFIG_MPC8555)
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#elif defined(CONFIG_ARCH_MPC8555)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_DDRC_GEN1
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#define CONFIG_SYS_FSL_DDRC_GEN1
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@ -77,7 +77,7 @@
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*/
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*/
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#define CPM_DATAONLY_BASE ((uint)128)
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#define CPM_DATAONLY_BASE ((uint)128)
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#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
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#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
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#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
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#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
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#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
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#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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#else /* MPC8540, MPC8560 */
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#else /* MPC8540, MPC8560 */
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@ -326,7 +326,7 @@ void lbc_sdram_init(void);
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#define LCRR_CLKDIV 0x0000001F
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#define LCRR_CLKDIV 0x0000001F
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#define LCRR_CLKDIV_SHIFT 0
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#define LCRR_CLKDIV_SHIFT 0
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#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
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#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555) || \
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
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defined(CONFIG_MPC8560)
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defined(CONFIG_MPC8560)
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#define LCRR_CLKDIV_2 0x00000002
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#define LCRR_CLKDIV_2 0x00000002
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#define LCRR_CLKDIV_4 0x00000004
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#define LCRR_CLKDIV_4 0x00000004
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@ -127,7 +127,7 @@ typedef struct ccsr_i2c {
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#if defined(CONFIG_ARCH_MPC8540) || \
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#if defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_ARCH_MPC8541) || \
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defined(CONFIG_ARCH_MPC8548) || \
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defined(CONFIG_ARCH_MPC8548) || \
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defined(CONFIG_MPC8555)
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defined(CONFIG_ARCH_MPC8555)
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/* DUART Registers */
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/* DUART Registers */
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typedef struct ccsr_duart {
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typedef struct ccsr_duart {
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u8 res1[1280];
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u8 res1[1280];
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@ -1831,7 +1831,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
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unsigned int clk_adjust; /* Clock adjust */
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unsigned int clk_adjust; /* Clock adjust */
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unsigned int ss_en = 0; /* Source synchronous enable */
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unsigned int ss_en = 0; /* Source synchronous enable */
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#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
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#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
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/* Per FSL Application Note: AN2805 */
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/* Per FSL Application Note: AN2805 */
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ss_en = 1;
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ss_en = 1;
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#endif
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#endif
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@ -47,7 +47,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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#if defined(CONFIG_MPC8555) || defined(CONFIG_ARCH_MPC8541)
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#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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#endif
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#endif
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@ -21,7 +21,7 @@ static struct input_config config;
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static int kbd_read_keys(struct input_config *config)
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static int kbd_read_keys(struct input_config *config)
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{
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{
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#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
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#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
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/* no ISR is used, so received chars must be polled */
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/* no ISR is used, so received chars must be polled */
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ps2ser_check();
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ps2ser_check();
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#endif
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#endif
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@ -17,7 +17,6 @@
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_CPM2 1 /* has CPM2 */
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#define CONFIG_CPM2 1 /* has CPM2 */
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#define CONFIG_MPC8555 1 /* MPC8555 specific */
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#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
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#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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@ -99,7 +99,7 @@ extern void pckbd_leds(unsigned char leds);
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#endif /* !CONFIG_DM_KEYBOARD */
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#endif /* !CONFIG_DM_KEYBOARD */
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#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
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#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
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defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
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int ps2ser_check(void);
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int ps2ser_check(void);
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#endif
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#endif
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@ -3141,7 +3141,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_VALUE
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CONFIG_MPC83XX_PCI2
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CONFIG_MPC83XX_PCI2
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CONFIG_MPC850
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CONFIG_MPC850
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CONFIG_MPC855
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CONFIG_MPC855
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CONFIG_MPC8555
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CONFIG_MPC8555CDS
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CONFIG_MPC8555CDS
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CONFIG_MPC8560
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CONFIG_MPC8560
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CONFIG_MPC8560ADS
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CONFIG_MPC8560ADS
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