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sh: sh_eth: Add support SH7724
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
e37ae40e9d
commit
3bb4cc312d
2 changed files with 61 additions and 24 deletions
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@ -1,8 +1,8 @@
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/*
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* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -371,7 +371,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(0, TFTR(port));
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outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
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outl(RMCR_RST, RMCR(port));
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#ifndef CONFIG_CPU_SH7757
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#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
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outl(0, RPADIR(port));
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#endif
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outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
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@ -393,16 +393,19 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(val, MALR(port));
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outl(RFLR_RFL_MIN, RFLR(port));
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#ifndef CONFIG_CPU_SH7757
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#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
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outl(0, PIPR(port));
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#endif
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#if !defined(CONFIG_CPU_SH7724)
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outl(APR_AP, APR(port));
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outl(MPR_MP, MPR(port));
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#ifdef CONFIG_CPU_SH7757
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outl(TPAUSER_UNLIMITED, TPAUSER(port));
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#else
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outl(TPAUSER_TPAUSE, TPAUSER(port));
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#endif
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#if defined(CONFIG_CPU_SH7763)
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outl(TPAUSER_TPAUSE, TPAUSER(port));
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#elif defined(CONFIG_CPU_SH7757)
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outl(TPAUSER_UNLIMITED, TPAUSER(port));
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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if (ret) {
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@ -412,33 +415,34 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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phy = port_info->phydev;
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phy_startup(phy);
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val = 0;
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/* Set the transfer speed */
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#ifdef CONFIG_CPU_SH7763
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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#ifdef CONFIG_CPU_SH7763
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outl(GECMR_100B, GECMR(port));
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#elif defined(CONFIG_CPU_SH7757)
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outl(1, RTRATE(port));
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#elif defined(CONFIG_CPU_SH7724)
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val = ECMR_RTM;
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#endif
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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#ifdef CONFIG_CPU_SH7763
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outl(GECMR_10B, GECMR(port));
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}
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#endif
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#if defined(CONFIG_CPU_SH7757)
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if (phy->speed == 100) {
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printf("100Base/");
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outl(1, RTRATE(port));
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} else if (phy->speed == 10) {
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printf("10Base/");
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#elif defined(CONFIG_CPU_SH7757)
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outl(0, RTRATE(port));
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}
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#endif
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}
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex) {
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printf("Full\n");
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outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
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outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
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} else {
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printf("Half\n");
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outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
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outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
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}
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return ret;
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@ -1,8 +1,8 @@
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/*
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* sh_eth.h - Driver for Renesas SuperH ethernet controler.
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -162,6 +162,32 @@ struct sh_eth_dev {
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#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
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#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
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#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
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#elif defined(CONFIG_CPU_SH7724)
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#define BASE_IO_ADDR 0xA4600000
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#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
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#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
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#define EDMR(port) (BASE_IO_ADDR + 0x0000)
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#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
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#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
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#define EESR(port) (BASE_IO_ADDR + 0x0028)
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#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
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#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
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#define TFTR(port) (BASE_IO_ADDR + 0x0048)
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#define FDR(port) (BASE_IO_ADDR + 0x0050)
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#define RMCR(port) (BASE_IO_ADDR + 0x0058)
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#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
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#define ECMR(port) (BASE_IO_ADDR + 0x0100)
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#define RFLR(port) (BASE_IO_ADDR + 0x0108)
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#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
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#define PIR(port) (BASE_IO_ADDR + 0x0120)
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#define APR(port) (BASE_IO_ADDR + 0x0154)
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#define MPR(port) (BASE_IO_ADDR + 0x0158)
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#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
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#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
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#define MALR(port) (BASE_IO_ADDR + 0x01c8)
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#endif
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/*
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@ -183,7 +209,7 @@ enum DMAC_M_BIT {
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EDMR_SRST = 0x03,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#elif defined CONFIG_CPU_SH7757
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#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
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EDMR_SRST = 0x01,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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@ -325,7 +351,8 @@ enum FCFTR_BIT {
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
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|| defined(CONFIG_CPU_SH7724)
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TD_TACT = 0x80000000,
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#else
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TD_TACT = 0x7fffffff,
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@ -350,6 +377,10 @@ enum FELIC_MODE_BIT {
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ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
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ECMR_PRM = 0x00000001,
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#ifdef CONFIG_CPU_SH7724
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ECMR_RTM = 0x00000010,
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#endif
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};
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#ifdef CONFIG_CPU_SH7763
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@ -357,6 +388,8 @@ enum FELIC_MODE_BIT {
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ECMR_TXF | ECMR_MCT)
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#elif CONFIG_CPU_SH7757
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#define ECMR_CHG_DM (ECMR_ZPF)
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#elif CONFIG_CPU_SH7724
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#endif
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