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Coding style cleanup

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-08-08 09:54:26 +02:00
parent a41de1f0d3
commit 3ba4c2d68f
3 changed files with 56 additions and 59 deletions
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1
board/freescale/m5329evb/m5329evb.c
View file

@ -86,4 +86,3 @@ int testdram(void)
return (0); return (0);
} }

103
board/freescale/m5329evb/nand.c
View file

@ -35,81 +35,80 @@ DECLARE_GLOBAL_DATA_PTR;
#include <nand.h> #include <nand.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#define SET_CLE 0x10 #define SET_CLE 0x10
#define CLR_CLE ~SET_CLE #define CLR_CLE ~SET_CLE
#define SET_ALE 0x08 #define SET_ALE 0x08
#define CLR_ALE ~SET_ALE #define CLR_ALE ~SET_ALE
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
u32 nand_baseaddr = (u32) this->IO_ADDR_W; u32 nand_baseaddr = (u32) this->IO_ADDR_W;
switch (cmd) { switch (cmd) {
case NAND_CTL_SETNCE: case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE: case NAND_CTL_CLRNCE:
break; break;
case NAND_CTL_SETCLE: case NAND_CTL_SETCLE:
nand_baseaddr |= SET_CLE; nand_baseaddr |= SET_CLE;
break; break;
case NAND_CTL_CLRCLE: case NAND_CTL_CLRCLE:
nand_baseaddr &= CLR_CLE; nand_baseaddr &= CLR_CLE;
break; break;
case NAND_CTL_SETALE: case NAND_CTL_SETALE:
nand_baseaddr |= SET_ALE; nand_baseaddr |= SET_ALE;
break; break;
case NAND_CTL_CLRALE: case NAND_CTL_CLRALE:
nand_baseaddr |= CLR_ALE; nand_baseaddr |= CLR_ALE;
break; break;
case NAND_CTL_SETWP: case NAND_CTL_SETWP:
fbcs->csmr2 |= CSMR_WP; fbcs->csmr2 |= CSMR_WP;
break; break;
case NAND_CTL_CLRWP: case NAND_CTL_CLRWP:
fbcs->csmr2 &= ~CSMR_WP; fbcs->csmr2 &= ~CSMR_WP;
break; break;
} }
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
} }
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
*((volatile u8 *)(this->IO_ADDR_W)) = byte; *((volatile u8 *)(this->IO_ADDR_W)) = byte;
} }
static u8 nand_read_byte(struct mtd_info *mtdinfo) static u8 nand_read_byte(struct mtd_info *mtdinfo)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
return (u8) (*((volatile u8 *)this->IO_ADDR_R)); return (u8) (*((volatile u8 *)this->IO_ADDR_R));
} }
static int nand_dev_ready(struct mtd_info *mtdinfo) static int nand_dev_ready(struct mtd_info *mtdinfo)
{ {
return 1; return 1;
} }
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
/* set up pin configuration */ /* set up pin configuration */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08; gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08; gpio->ppd_timer |= 0x08;
gpio->pclrr_timer = 0; gpio->pclrr_timer = 0;
gpio->podr_timer = 0; gpio->podr_timer = 0;
nand->chip_delay = 50; nand->chip_delay = 50;
nand->eccmode = NAND_ECC_SOFT; nand->eccmode = NAND_ECC_SOFT;
nand->hwcontrol = nand_hwcontrol; nand->hwcontrol = nand_hwcontrol;
nand->read_byte = nand_read_byte; nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte; nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready; nand->dev_ready = nand_dev_ready;
return 0; return 0;
} }
#endif #endif

11
cpu/mcf532x/cpu_init.c
View file

@ -71,35 +71,35 @@ void cpu_init_f(void)
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
/* Latch chipselect */ /* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1; gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CFG_CS1_BASE; fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL; fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK; fbcs->csmr1 = CFG_CS1_MASK;
#endif #endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2; gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CFG_CS2_BASE; fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL; fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK; fbcs->csmr2 = CFG_CS2_MASK;
#endif #endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3; gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CFG_CS3_BASE; fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL; fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK; fbcs->csmr3 = CFG_CS3_MASK;
#endif #endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4; gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CFG_CS4_BASE; fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL; fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK; fbcs->csmr4 = CFG_CS4_MASK;
#endif #endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5; gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CFG_CS5_BASE; fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL; fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK; fbcs->csmr5 = CFG_CS5_MASK;
@ -139,4 +139,3 @@ void uart_port_conf(void)
break; break;
} }
} }