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include: delete unused header files

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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada 2014-01-08 20:11:27 +09:00 committed by Tom Rini
parent 853ce2ee9c
commit 3b98b57fa7
20 changed files with 0 additions and 2473 deletions
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77
include/amba_clcd.h
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@ -1,77 +0,0 @@
/*
* Register definitions for the AMBA CLCD logic cell.
*
* derived from David A Rusling, although rearranged as a C structure
* linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
*
* Copyright (C) 2001 ARM Limited
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/*
* CLCD Controller Internal Register addresses
*/
struct clcd_registers {
u32 tim0; /* 0x00 */
u32 tim1;
u32 tim2;
u32 tim3;
u32 ubas; /* 0x10 */
u32 lbas;
#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
u32 ienb;
u32 cntl;
#else /* Someone rearranged these two registers on the Versatile */
u32 cntl;
u32 ienb;
#endif
u32 stat; /* 0x20 */
u32 intr;
u32 ucur;
u32 lcur;
u32 unused[0x74]; /* 0x030..0x1ff */
u32 palette[0x80]; /* 0x200..0x3ff */
};
/* Bit definition for TIM2 */
#define TIM2_CLKSEL (1 << 5)
#define TIM2_IVS (1 << 11)
#define TIM2_IHS (1 << 12)
#define TIM2_IPC (1 << 13)
#define TIM2_IOE (1 << 14)
#define TIM2_BCD (1 << 26)
/* Bit definitions for control register */
#define CNTL_LCDEN (1 << 0)
#define CNTL_LCDBPP1 (0 << 1)
#define CNTL_LCDBPP2 (1 << 1)
#define CNTL_LCDBPP4 (2 << 1)
#define CNTL_LCDBPP8 (3 << 1)
#define CNTL_LCDBPP16 (4 << 1)
#define CNTL_LCDBPP16_565 (6 << 1)
#define CNTL_LCDBPP24 (5 << 1)
#define CNTL_LCDBW (1 << 4)
#define CNTL_LCDTFT (1 << 5)
#define CNTL_LCDMONO8 (1 << 6)
#define CNTL_LCDDUAL (1 << 7)
#define CNTL_BGR (1 << 8)
#define CNTL_BEBO (1 << 9)
#define CNTL_BEPO (1 << 10)
#define CNTL_LCDPWR (1 << 11)
#define CNTL_LCDVCOMP(x) ((x) << 12)
#define CNTL_LDMAFIFOTIME (1 << 15)
#define CNTL_WATERMARK (1 << 16)
/* u-boot specific: information passed by the board file */
struct clcd_config {
struct clcd_registers *address;
u32 tim0;
u32 tim1;
u32 tim2;
u32 tim3;
u32 cntl;
unsigned long pixclock;
};

28
include/asm-generic/global_data_flags.h
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/*
* transitional header until we merge global_data.h
*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
#define __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
/*
* Global Data Flags
*
* Note: The low 16 bits are expected for common code. If your arch
* really needs to add your own, use the high 16bits.
*/
#define GD_FLG_RELOC 0x0001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x0002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x0004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x0008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x0010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x0020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x0040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x0080 /* Environment imported into hash table */
#endif

68
include/at45.h
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#ifndef _AT45_H_
#define _AT45_H_
#ifdef CONFIG_DATAFLASH_MMC_SELECT
extern void AT91F_SelectMMC(void);
extern void AT91F_SelectSPI(void);
extern int AT91F_GetMuxStatus(void);
#endif
extern void AT91F_SpiInit(void);
extern void AT91F_SpiEnable(int cs);
extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress);
extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
AT91PS_DataflashDesc pDesc);
extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
AT91PS_DataflashDesc pDataFlashDesc,
unsigned int timeout);
extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead );
extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite);
extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite );
extern AT91S_DataFlashStatus AT91F_PageErase(
AT91PS_DataFlash pDataFlash,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_BlockErase(
AT91PS_DataFlash pDataFlash,
unsigned int block);
extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest );
extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size);
extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest,
int size );
extern int AT91F_DataFlashRead(
AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size,
char *buffer);
extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
#endif

114
include/at91rm9200_i2c.h
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/* ---------------------------------------------------------------------------- */
/* ATMEL Microcontroller Software Support - ROUSSET - */
/* ---------------------------------------------------------------------------- */
/* The software is delivered "AS IS" without warranty or condition of any */
/* kind, either express, implied or statutory. This includes without */
/* limitation any warranty or condition with respect to merchantability or */
/* fitness for any particular purpose, or against the infringements of */
/* intellectual property rights of others. */
/* ---------------------------------------------------------------------------- */
/* File Name : at91rm9200_i2c.h */
/* Object : AT91RM9200 / TWI definitions */
/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */
/* */
/* ---------------------------------------------------------------------------- */
#ifndef AT91RM9200_TWI_H
#define AT91RM9200_TWI_H
/* ******************************************************************************/
/* SOFTWARE API DEFINITION FOR Two-wire Interface */
/* ******************************************************************************/
#ifndef __ASSEMBLY__
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; /* Control Register */
AT91_REG TWI_MMR; /* Master Mode Register */
AT91_REG TWI_SMR; /* Slave Mode Register */
AT91_REG TWI_IADR; /* Internal Address Register */
AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
AT91_REG Reserved0[3];
AT91_REG TWI_SR; /* Status Register */
AT91_REG TWI_IER; /* Interrupt Enable Register */
AT91_REG TWI_IDR; /* Interrupt Disable Register */
AT91_REG TWI_IMR; /* Interrupt Mask Register */
AT91_REG TWI_RHR; /* Receive Holding Register */
AT91_REG TWI_THR; /* Transmit Holding Register */
AT91_REG Reserved1[50];
AT91_REG TWI_RPR; /* Receive Pointer Register */
AT91_REG TWI_RCR; /* Receive Counter Register */
AT91_REG TWI_TPR; /* Transmit Pointer Register */
AT91_REG TWI_TCR; /* Transmit Counter Register */
AT91_REG TWI_RNPR; /* Receive Next Pointer Register */
AT91_REG TWI_RNCR; /* Receive Next Counter Register */
AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */
AT91_REG TWI_TNCR; /* Transmit Next Counter Register */
AT91_REG TWI_PTCR; /* PDC Transfer Control Register */
AT91_REG TWI_PTSR; /* PDC Transfer Status Register */
} AT91S_TWI, *AT91PS_TWI;
#endif
/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */
#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */
#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */
#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */
#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */
#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */
#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */
/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */
#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */
#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */
/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */
/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */
#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */
#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */
/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */
#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */
#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/
#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */
#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */
#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */
#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */
#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */
#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */
#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */
/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
/*
i2c Support for Atmel's AT91RM9200 Two-Wire Interface
(c) Rick Bronson
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91_I2C_H
#define AT91_I2C_H
#define AT91C_TWI_CLOCK 100000
#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */
#if (AT91C_TWI_SCLOCK % 10) >= 5
#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
#else
#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
#endif
#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16)
#endif /* __ASSEMBLY__ */
#endif /* AT91RM9200_TWI_H */

50
include/at91rm9200_net.h
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@ -1,50 +0,0 @@
/*
* Ethernet: An implementation of the Ethernet Device Driver suite for the
* uClinux 2.0.38 operating system. This Driver has been developed
* for AT75C220 board.
*
* NOTE: The driver is implemented for one MAC
*
* Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001
*
* Authors: Lineo Inc <www.lineo.com>
*
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91RM9200_ETHERNET
#define AT91RM9200_ETHERNET
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#define ETHERNET_ADDRESS_SIZE 6
typedef unsigned char UCHAR;
/* Interface to drive the physical layer */
typedef struct _AT91S_PhyOps
{
unsigned char (*Init)(AT91S_EMAC *pmac);
unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac);
unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
} AT91S_PhyOps,*AT91PS_PhyOps;
#define EMAC_DESC_DONE 0x00000001 /* ownership bit */
#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
/****************** function prototypes **********************/
/* MII functions */
void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
#endif /* AT91RM9200_ETHERNET */

88
include/bcm5221.h
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/*
* Broadcom BCM5221 Ethernet PHY
*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define BCM5221_BMCR 0 /* Basic Mode Control Register */
#define BCM5221_BMSR 1 /* Basic Mode Status Register */
#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */
#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */
#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */
#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */
#define BCM5221_INTR 26 /* Interrupt Register */
/* --Bit definitions: BCM5221_BMCR */
#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define BCM5221_AUTONEG (1 << 12)
#define BCM5221_POWER_DOWN (1 << 11)
#define BCM5221_ISOLATE (1 << 10)
#define BCM5221_RESTART_AUTONEG (1 << 9)
#define BCM5221_DUPLEX_MODE (1 << 8)
#define BCM5221_COLLISION_TEST (1 << 7)
/*--Bit definitions: BCM5221_BMSR */
#define BCM5221_100BASE_T4 (1 << 15)
#define BCM5221_100BASE_TX_FD (1 << 14)
#define BCM5221_100BASE_TX_HD (1 << 13)
#define BCM5221_10BASE_T_FD (1 << 12)
#define BCM5221_10BASE_T_HD (1 << 11)
#define BCM5221_MF_PREAMB_SUPPR (1 << 6)
#define BCM5221_AUTONEG_COMP (1 << 5)
#define BCM5221_REMOTE_FAULT (1 << 4)
#define BCM5221_AUTONEG_ABILITY (1 << 3)
#define BCM5221_LINK_STATUS (1 << 2)
#define BCM5221_JABBER_DETECT (1 << 1)
#define BCM5221_EXTEND_CAPAB (1 << 0)
/*--definitions: BCM5221_PHYID1 */
#define BCM5221_PHYID1_OUI 0x1018
#define BCM5221_LSB_MASK 0x3F
/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
#define BCM5221_NP (1 << 15)
#define BCM5221_ACK (1 << 14)
#define BCM5221_RF (1 << 13)
#define BCM5221_FCS (1 << 10)
#define BCM5221_T4 (1 << 9)
#define BCM5221_TX_FDX (1 << 8)
#define BCM5221_TX_HDX (1 << 7)
#define BCM5221_10_FDX (1 << 6)
#define BCM5221_10_HDX (1 << 5)
#define BCM5221_AN_IEEE_802_3 0x0001
/*--Bit definitions: BCM5221_ANER */
#define BCM5221_PDF (1 << 4)
#define BCM5221_LP_NP_ABLE (1 << 3)
#define BCM5221_NP_ABLE (1 << 2)
#define BCM5221_PAGE_RX (1 << 1)
#define BCM5221_LP_AN_ABLE (1 << 0)
/*--Bit definitions: BCM5221_ACSR */
#define BCM5221_100 (1 << 1)
#define BCM5221_FDX (1 << 0)
/*--Bit definitions: BCM5221_INTR */
#define BCM5221_FDX_LED (1 << 15)
#define BCM5221_INTR_ENABLE (1 << 14)
#define BCM5221_FDX_MASK (1 << 11)
#define BCM5221_SPD_MASK (1 << 10)
#define BCM5221_LINK_MASK (1 << 9)
#define BCM5221_INTR_MASK (1 << 8)
#define BCM5221_FDX_CHG (1 << 3)
#define BCM5221_SPD_CHG (1 << 2)
#define BCM5221_LINK_CHG (1 << 1)
#define BCM5221_INTR_STATUS (1 << 0)
/****************** function prototypes **********************/
unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);

35
include/configs/AdderUSB.h
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/*
* Copyright (C) 2006 CodeHermit.
* Bryan O'Donoghue <bodonoghue@codehermit.ie>
*
* Provides support for USB console on the Analogue & Micro Adder87x
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ADDERUSB__
#define __ADDERUSB__
/* Include the board port */
#include "Adder.h"
#define CONFIG_USB_DEVICE /* Include UDC driver */
#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */
/* If you have a USB-IF assigned VendorID then you may wish to define
* your own vendor specific values either in BoardName.h or directly in
* usbd_vendor_info.h
*/
/*
#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
#define CONFIG_USBD_VENDORID 0xFFFF
#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
*/
#endif /* __ADDERUSB_H__ */

190
include/configs/EXBITGEN.h
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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
/* I2C configuration */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
/* environment is in EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM 1
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NVRAM
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */
#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */
#endif
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
/* Explanation:
autbooting is altogether disabled and cannot be
enabled if CONFIG_BOOTDELAY is negative.
If you want shorter bootdelay, then
- "setenv bootdelay <delay>" to the proper value
*/
#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000"
#define CONFIG_BOOTARGS "root=/dev/ram " \
"ramdisk_size=32768 " \
"console=ttyS0,115200 " \
"ram=128M debug"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_PPC4xx_EMAC
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/* UART configuration */
#define CONFIG_SYS_BASE_BAUD 691200
/* Default baud rate */
#define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#undef CONFIG_PCI /* no pci support */
/*-----------------------------------------------------------------------
* External peripheral base address
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH0_BASE 0xFFF80000
#define CONFIG_SYS_FLASH0_SIZE 0x00080000
#define CONFIG_SYS_FLASH1_BASE 0x20000000
#define CONFIG_SYS_FLASH1_SIZE 0x02000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_RAMSTART
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */
#endif
/* On Chip Memory location/size */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
/* Global info and initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
#endif /* __CONFIG_H */

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include/configs/MVS1.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_MVS 1 /* ...on a MVsensor module */
#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate */
#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
#define CONFIG_PREBOOT "echo;" \
"echo To mount root over NFS use \"run bootnet\";" \
"echo To mount root from FLASH use \"run bootflash\";" \
"echo"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_VENDOREX
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_RUN
/*
* Miscellaneous configurable options
*/
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CONFIG_SYS_IMMR 0xFFF00000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x40000000
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
*/
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CONFIG_SYS_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CONFIG_SYS_DER 0x2002000F*/
#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
#undef FLASH_BASE1_PRELIM
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing:
*/
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
/*
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_5_CLK | OR_EHTR)
*/
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#ifdef CONFIG_MVS_16BIT_FLASH
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
#else
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
#endif
#undef CONFIG_SYS_OR1_REMAP
#undef CONFIG_SYS_OR1_PRELIM
#undef CONFIG_SYS_BR1_PRELIM
/*
* BR2/3 and OR2/3 (SDRAM)
*
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#undef SDRAM_BASE3_PRELIM
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#undef CONFIG_SYS_OR3_PRELIM
#undef CONFIG_SYS_BR3_PRELIM
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
#define CONFIG_SYS_MAMR_PTA 98
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#endif /* __CONFIG_H */

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include/configs/ORSG.h
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/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_ORSG 1 /* ...on a ORSG board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "go fff00100"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
/* resource configuration */
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
#else /* Use EEPROM for environment variables */
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
#endif
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Flash Bank 1) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (PLD - FPGA-boot) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (PLD - OSL) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 4 (Spartan2 1) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
/* Memory Bank 5 (Spartan2 2) initialization */
#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
/* Memory Bank 6 (Virtex 1) initialization */
#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
/* Memory Bank 7 (Virtex 2) initialization */
#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#endif /* __CONFIG_H */

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include/configs/mpq101.h
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/*
* Copyright 2011 Alex Dubov <oakad@yahoo.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Merury Computers MPQ101 board configuration file
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_36BIT
# define CONFIG_PHYS_64BIT
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 /* MPC8548 specific */
#define CONFIG_MPQ101 /* MPQ101 board specific */
#define CONFIG_SYS_SRIO /* enable serial RapidIO */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW /* Use common FSL init code */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_PANIC_HANG
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS
#ifdef CONFIG_PHYS_64BIT
# define CONFIG_ADDR_MAP
# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SYS_FSL_DDR2
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/* Fixed 512MB DDR2 parameters */
#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
#define CONFIG_SYS_DDR_TIMING_3 0x00010000
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432
#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
#define CONFIG_SYS_DDR_TIMING_2 0x03984cce
#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
#define CONFIG_SYS_DDR_MODE_1 0x00400442
#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432
#define CONFIG_SYS_DDR_MODE_2 0x00000000
#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000
#define CONFIG_SYS_DDR_INTERVAL 0x08200100
#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */
#define CONFIG_SYS_DDR_CONTROL2 0x04400000
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0ffffffc
/*
* RAM definitions
*/
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
/*
* FLASH on the Local Bus
* One bank, 128M, using the CFI driver.
*/
#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
#ifdef CONFIG_PHYS_64BIT
# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
#else
# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
/* 0xf8001801 */
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_32 | BR_V)
/* 0xf8006ff7 */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
| OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash.
*/
#define CONFIG_ASSUME_AMD_FLASH
/*
* Environment parameters
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_USE_PPCENV
#define ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
#define CONFIG_ENV_SIZE 0x800
/* Environment at the start of flash sector, before text. */
#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_TEXT_BASE 0xfffc0800
#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds"
/*
* Cypress CY7C67200 USB controller on the Local Bus.
* Not supported by u-boot at present.
*/
#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
#ifdef CONFIG_PHYS_64BIT
# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
#else
# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
#endif
/* 0xf0001001 */
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
| BR_PS_16 | BR_V)
/* fffff002 */
#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
| OR_GPCM_BCTLD | OR_GPCM_EHTR)
/*
* Serial Ports
*/
#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \
19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/*
* I2C buses and peripherals
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* I2C RTC - M41T81 */
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
/* I2C EEPROM - 24C256 */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* RapidIO MMU
*/
#ifdef CONFIG_SYS_SRIO
# define CONFIG_SRIO1
# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
# ifdef CONFIG_PHYS_64BIT
# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
# else
# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
# endif
#endif
/*
* Ethernet
*/
#ifdef CONFIG_TSEC_ENET
# define CONFIG_MII /* MII PHY management */
# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
# define CONFIG_TSEC1
# define CONFIG_TSEC1_NAME "eTSEC0"
# define TSEC1_PHY_ADDR 0x10
# define TSEC1_PHYIDX 0
# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
# define CONFIG_TSEC2
# define CONFIG_TSEC2_NAME "eTSEC1"
# define TSEC2_PHY_ADDR 0x11
# define TSEC2_PHYIDX 0
# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
# define CONFIG_TSEC3
# define CONFIG_TSEC3_NAME "eTSEC2"
# define TSEC3_PHY_ADDR 0x12
# define TSEC3_PHYIDX 0
# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
# define CONFIG_TSEC4
# define CONFIG_TSEC4_NAME "eTSEC3"
# define TSEC4_PHY_ADDR 0x13
# define TSEC4_PHYIDX 0
# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
# define CONFIG_ETHPRIME "eTSEC0"
# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_JFFS2
/*
* Miscellaneous configurable options
*/
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_FIT /* new uImage format support */
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */
/* Console I/O Buffer Size */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024
#else
# define CONFIG_SYS_CBSIZE 256
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Basic Environment Configuration
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
/*default location for tftp and bootm*/
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#endif /* __CONFIG_H */

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include/configs/tb0229.h
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/*
* (C) Copyright 2003
* Masami Komiya <mkomiya@sonare.it>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Config header file for TANBAC TB0229 board using an VR4131 CPU module
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_TB0229 1 /* on a TB0229 Board */
#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */
#endif
#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */
#define CONFIG_CONS_INDEX 1
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BAUDRATE 115200
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \
"echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo Type \\\"run flash_local\\\" to mount local root filesystem;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netboot=dhcp;tftp;run netargs; bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \
"localargs=setenv bootargs root=1F02 ip=dhcp\0" \
"addmisc=setenv bootargs ${bootargs} " \
"console=ttyS0,${baudrate} " \
"read-only=readonly\0" \
"netargs=run nfsargs addmisc\0" \
"flash_nfs=run nfsargs addmisc;" \
"bootm ${kernel_addr}\0" \
"flash_local=run localargs addmisc;" \
"bootm ${kernel_addr}\0" \
"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \
"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
"run addmisc;" \
"bootm 80400000 80600000\0" \
"rootpath=/export/miniroot-mipsel\0" \
"autoload=no\0" \
"kernel_addr=BFC60000\0" \
"ramdisk_addr=B0100000\0" \
"u-boot=u-boot.bin\0" \
"bootfile=uImage\0" \
"load=dhcp;tftp 80400000 ${u-boot}\0" \
"load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \
"update_uboot=run load;" \
"protect off BFC00000 BFC3FFFF;" \
"erase BFC00000 BFC3FFFF;" \
"cp.b 80400000 BFC00000 ${filesize}\0" \
"update_kernel=run load_kernel;" \
"erase BFC60000 BFD5FFFF;" \
"cp.b 80400000 BFC60000 ${filesize}\0" \
"initenv=erase bfc40000 bfc5ffff\0" \
""
/*#define CONFIG_BOOTCOMMAND "run flash_local" */
#define CONFIG_BOOTCOMMAND "run netboot"
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI
#define CONFIG_CMD_ELF
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_MALLOC_LEN 128*1024
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4)
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x80800000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_ADDR 0xBFC40000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_NR_DRAM_BANKS 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Serial Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 18432000
#define CONFIG_SYS_NS16550_COM1 0xaf000800
/*-----------------------------------------------------------------------
* PCI stuff
*/
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_RTL8139
#endif /* __CONFIG_H */

19
include/cramfs/cramfs_fs_sb.h
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#ifndef _CRAMFS_FS_SB
#define _CRAMFS_FS_SB
/*
* cramfs super-block data in memory
*/
struct cramfs_sb_info {
unsigned long magic;
unsigned long size;
unsigned long blocks;
unsigned long files;
unsigned long flags;
#ifdef CONFIG_CRAMFS_LINEAR
unsigned long linear_phys_addr;
char * linear_virt_addr;
#endif
};
#endif

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include/da9030.h
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/*
* (C) Copyright 2006 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* DA9030 register definitions */
#define CID 0x00
#define EVENT_A 0x01
#define EVENT_B 0x02
#define EVENT_C 0x03
#define STATUS 0x04
#define IRQ_MASK_A 0x05
#define IRQ_MASK_B 0x06
#define IRQ_MASK_C 0x07
#define SYS_CONTROL_A 0x08
#define SYS_CONTROL_B 0x09
#define FAULT_LOG 0x0A
#define LDO_10_11 0x10
#define LDO_15 0x11
#define LDO_14_16 0x12
#define LDO_18_19 0x13
#define LDO_17_SIMCP0 0x14
#define BUCK2_DVC1 0x15
#define BUCK2_DVC2 0x16
#define REG_CONTROL_1_17 0x17
#define REG_CONTROL_2_18 0x18
#define USBPUMP 0x19
#define SLEEP_CONTROL 0x1A
#define STARTUP_CONTROL 0x1B
#define LED1_CONTROL 0x20
#define LED2_CONTROL 0x21
#define LED3_CONTROL 0x22
#define LED4_CONTROL 0x23
#define LEDPC_CONTROL 0x24
#define WLED_CONTROL 0x25
#define MISC_CONTROLA 0x26
#define MISC_CONTROLB 0x27
#define CHARGE_CONTROL 0x28
#define CCTR_CONTROL 0x29
#define TCTR_CONTROL 0x2A
#define CHARGE_PULSE 0x2B
/* ... some missing ...*/
#define LDO1 0x90
#define LDO2_3 0x91
#define LDO4_5 0x92
#define LDO6_SIMCP 0x93
#define LDO7_8 0x94
#define LDO9_12 0x95
#define BUCK 0x96
#define REG_CONTROL_1_97 0x97
#define REG_CONTROL_2_98 0x98
#define REG_SLEEP_CONTROL1 0x99
#define REG_SLEEP_CONTROL2 0x9A
#define REG_SLEEP_CONTROL3 0x9B
#define ADC_MAN_CONTROL 0xA0
#define ADC_AUTO_CONTROL 0xA1
#define VBATMON 0xA2
#define VBATMONTXMON 0xA3
#define TBATHIGHP 0xA4
#define TBATHIGHN 0xA5
#define TBATLOW 0xA6
#define MAN_RES 0xB0
#define VBAT_RES 0xB1
#define VBATMIN_RES 0xB2
#define VBATMINTXON_RES 0xB3
#define ICHMAX_RES 0xB4
#define ICHMIN_RES 0xB5
#define ICHAVERAGE_RES 0xB6
#define VCHMAX_RES 0xB7
#define VCHMIN_RES 0xB8
#define TBAT_RES 0xB9
#define ADC_IN4_RES 0xBA
#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */
#define STATUS_PWREN1 (1<<1) /* PWREN1 value */
#define STATUS_EXTON (1<<2) /* EXTON value */
#define STATUS_CHDET (1<<3) /* Charger detection status */
#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */
#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */
#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */
#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */
#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1
#define SYS_CONTROL_A_SHUT_DOWN (1<<1)
#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
#define SYS_CONTROL_A_WATCHDOG (1<<7)
#define MISC_CONTROLB_USB_INT_RISING (1<<2)
#define MISC_CONTROLB_SESSION_VALID_EN (1<<3)
#define USB_PUMP_USBVE (1<<0)
#define USB_PUMP_USBVEP (1<<1)
#define USB_PUMP_SRP_DETECT (1<<2)
#define USB_PUMP_SESSION_VALID (1<<3)
#define USB_PUMP_VBUS_VALID_4_0 (1<<4)
#define USB_PUMP_VBUS_VALID_4_4 (1<<5)
#define USB_PUMP_EN_USBVE (1<<6)
#define USB_PUMP_EN_USBVEP (1<<7)

127
include/dm9161.h
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/*
* NOTE: DAVICOM ethernet Physical layer
*
* Version: @(#)DM9161.h 1.0.0 01/10/2001
*
* Authors: ATMEL Rousset
*
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
#define DM9161_BMCR 0 /* Basic Mode Control Register */
#define DM9161_BMSR 1 /* Basic Mode Status Register */
#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
#define DM9161_DSCR 16 /* Specified Configuration Register */
#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
#define DM9161_MDINTR 21 /* Specified Interrupt Register */
#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
/* --Bit definitions: DM9161_BMCR */
#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define DM9161_AUTONEG (1 << 12)
#define DM9161_POWER_DOWN (1 << 11)
#define DM9161_ISOLATE (1 << 10)
#define DM9161_RESTART_AUTONEG (1 << 9)
#define DM9161_DUPLEX_MODE (1 << 8)
#define DM9161_COLLISION_TEST (1 << 7)
/*--Bit definitions: DM9161_BMSR */
#define DM9161_100BASE_TX (1 << 15)
#define DM9161_100BASE_TX_FD (1 << 14)
#define DM9161_100BASE_TX_HD (1 << 13)
#define DM9161_10BASE_T_FD (1 << 12)
#define DM9161_10BASE_T_HD (1 << 11)
#define DM9161_MF_PREAMB_SUPPR (1 << 6)
#define DM9161_AUTONEG_COMP (1 << 5)
#define DM9161_REMOTE_FAULT (1 << 4)
#define DM9161_AUTONEG_ABILITY (1 << 3)
#define DM9161_LINK_STATUS (1 << 2)
#define DM9161_JABBER_DETECT (1 << 1)
#define DM9161_EXTEND_CAPAB (1 << 0)
/*--definitions: DM9161_PHYID1 */
#define DM9161_PHYID1_OUI 0x606E
#define DM9161_LSB_MASK 0x3F
/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
#define DM9161_NP (1 << 15)
#define DM9161_ACK (1 << 14)
#define DM9161_RF (1 << 13)
#define DM9161_FCS (1 << 10)
#define DM9161_T4 (1 << 9)
#define DM9161_TX_FDX (1 << 8)
#define DM9161_TX_HDX (1 << 7)
#define DM9161_10_FDX (1 << 6)
#define DM9161_10_HDX (1 << 5)
#define DM9161_AN_IEEE_802_3 0x0001
/*--Bit definitions: DM9161_ANER */
#define DM9161_PDF (1 << 4)
#define DM9161_LP_NP_ABLE (1 << 3)
#define DM9161_NP_ABLE (1 << 2)
#define DM9161_PAGE_RX (1 << 1)
#define DM9161_LP_AN_ABLE (1 << 0)
/*--Bit definitions: DM9161_DSCR */
#define DM9161_BP4B5B (1 << 15)
#define DM9161_BP_SCR (1 << 14)
#define DM9161_BP_ALIGN (1 << 13)
#define DM9161_BP_ADPOK (1 << 12)
#define DM9161_REPEATER (1 << 11)
#define DM9161_TX (1 << 10)
#define DM9161_RMII_ENABLE (1 << 8)
#define DM9161_F_LINK_100 (1 << 7)
#define DM9161_SPLED_CTL (1 << 6)
#define DM9161_COLLED_CTL (1 << 5)
#define DM9161_RPDCTR_EN (1 << 4)
#define DM9161_SM_RST (1 << 3)
#define DM9161_MFP SC (1 << 2)
#define DM9161_SLEEP (1 << 1)
#define DM9161_RLOUT (1 << 0)
/*--Bit definitions: DM9161_DSCSR */
#define DM9161_100FDX (1 << 15)
#define DM9161_100HDX (1 << 14)
#define DM9161_10FDX (1 << 13)
#define DM9161_10HDX (1 << 12)
/*--Bit definitions: DM9161_10BTCSR */
#define DM9161_LP_EN (1 << 14)
#define DM9161_HBE (1 << 13)
#define DM9161_SQUELCH (1 << 12)
#define DM9161_JABEN (1 << 11)
#define DM9161_10BT_SER (1 << 10)
#define DM9161_POLR (1 << 0)
/*--Bit definitions: DM9161_MDINTR */
#define DM9161_INTR_PEND (1 << 15)
#define DM9161_FDX_MASK (1 << 11)
#define DM9161_SPD_MASK (1 << 10)
#define DM9161_LINK_MASK (1 << 9)
#define DM9161_INTR_MASK (1 << 8)
#define DM9161_FDX_CHANGE (1 << 4)
#define DM9161_SPD_CHANGE (1 << 3)
#define DM9161_LINK_CHANGE (1 << 2)
#define DM9161_INTR_STATUS (1 << 0)
/****************** function prototypes **********************/
unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);

13
include/faraday/ftsdc021.h
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/*
* (C) Copyright 2013 Faraday Technology
* Dante Su <dantesu@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FTSDC021_H
#define __FTSDC021_H
int ftsdc021_sdhci_init(u32 regbase);
#endif /* __FTSDC021_H */

75
include/ks8721.h
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/*
* NOTE: MICREL ethernet Physical layer
*
* Version: KS8721.h
*
* Authors: Eric Benard (based on dm9161.h)
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
#define KS8721_BMCR 0
#define KS8721_BMSR 1
#define KS8721_PHYID1 2
#define KS8721_PHYID2 3
#define KS8721_ANAR 4
#define KS8721_ANLPAR 5
#define KS8721_ANER 6
#define KS8721_RECR 15
#define KS8721_MDINTR 27
#define KS8721_100BT 31
/* --Bit definitions: KS8721_BMCR */
#define KS8721_RESET (1 << 15)
#define KS8721_LOOPBACK (1 << 14)
#define KS8721_SPEED_SELECT (1 << 13)
#define KS8721_AUTONEG (1 << 12)
#define KS8721_POWER_DOWN (1 << 11)
#define KS8721_ISOLATE (1 << 10)
#define KS8721_RESTART_AUTONEG (1 << 9)
#define KS8721_DUPLEX_MODE (1 << 8)
#define KS8721_COLLISION_TEST (1 << 7)
#define KS8721_DISABLE (1 << 0)
/*--Bit definitions: KS8721_BMSR */
#define KS8721_100BASE_T4 (1 << 15)
#define KS8721_100BASE_TX_FD (1 << 14)
#define KS8721_100BASE_T4_HD (1 << 13)
#define KS8721_10BASE_T_FD (1 << 12)
#define KS8721_10BASE_T_HD (1 << 11)
#define KS8721_MF_PREAMB_SUPPR (1 << 6)
#define KS8721_AUTONEG_COMP (1 << 5)
#define KS8721_REMOTE_FAULT (1 << 4)
#define KS8721_AUTONEG_ABILITY (1 << 3)
#define KS8721_LINK_STATUS (1 << 2)
#define KS8721_JABBER_DETECT (1 << 1)
#define KS8721_EXTEND_CAPAB (1 << 0)
/*--Bit definitions: KS8721_PHYID */
#define KS8721_PHYID_OUI 0x0885
#define KS8721_LSB_MASK 0x3F
#define KS8721BL_MODEL 0x21
#define KS8721_MODELMASK 0x3F0
#define KS8721BL_REV 0x9
#define KS8721_REVMASK 0xF
/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
#define KS8721_NP (1 << 15)
#define KS8721_ACK (1 << 14)
#define KS8721_RF (1 << 13)
#define KS8721_PAUSE (1 << 10)
#define KS8721_T4 (1 << 9)
#define KS8721_TX_FDX (1 << 8)
#define KS8721_TX_HDX (1 << 7)
#define KS8721_10_FDX (1 << 6)
#define KS8721_10_HDX (1 << 5)
#define KS8721_AN_IEEE_802_3 0x0001
/****************** function prototypes **********************/
unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac);
unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char ks8721_initphy(AT91PS_EMAC p_mac);

89
include/linux/mtd/inftl-user.h
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/*
* $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $
*
* Parts of INFTL headers shared with userspace
*
*/
#ifndef __MTD_INFTL_USER_H__
#define __MTD_INFTL_USER_H__
#define OSAK_VERSION 0x5120
#define PERCENTUSED 98
#define SECTORSIZE 512
/* Block Control Information */
struct inftl_bci {
uint8_t ECCsig[6];
uint8_t Status;
uint8_t Status1;
} __attribute__((packed));
struct inftl_unithead1 {
uint16_t virtualUnitNo;
uint16_t prevUnitNo;
uint8_t ANAC;
uint8_t NACs;
uint8_t parityPerField;
uint8_t discarded;
} __attribute__((packed));
struct inftl_unithead2 {
uint8_t parityPerField;
uint8_t ANAC;
uint16_t prevUnitNo;
uint16_t virtualUnitNo;
uint8_t NACs;
uint8_t discarded;
} __attribute__((packed));
struct inftl_unittail {
uint8_t Reserved[4];
uint16_t EraseMark;
uint16_t EraseMark1;
} __attribute__((packed));
union inftl_uci {
struct inftl_unithead1 a;
struct inftl_unithead2 b;
struct inftl_unittail c;
};
struct inftl_oob {
struct inftl_bci b;
union inftl_uci u;
};
/* INFTL Media Header */
struct INFTLPartition {
__u32 virtualUnits;
__u32 firstUnit;
__u32 lastUnit;
__u32 flags;
__u32 spareUnits;
__u32 Reserved0;
__u32 Reserved1;
} __attribute__((packed));
struct INFTLMediaHeader {
char bootRecordID[8];
__u32 NoOfBootImageBlocks;
__u32 NoOfBinaryPartitions;
__u32 NoOfBDTLPartitions;
__u32 BlockMultiplierBits;
__u32 FormatFlags;
__u32 OsakVersion;
__u32 PercentUsed;
struct INFTLPartition Partitions[4];
} __attribute__((packed));
/* Partition flag types */
#define INFTL_BINARY 0x20000000
#define INFTL_BDTL 0x40000000
#define INFTL_LAST 0x80000000
#endif /* __MTD_INFTL_USER_H__ */

35
include/linux/mtd/jffs2-user.h
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/*
* $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $
*
* JFFS2 definitions for use in user space only
*/
#ifndef __JFFS2_USER_H__
#define __JFFS2_USER_H__
/* This file is blessed for inclusion by userspace */
#include <linux/jffs2.h>
#include <endian.h>
#include <byteswap.h>
#undef cpu_to_je16
#undef cpu_to_je32
#undef cpu_to_jemode
#undef je16_to_cpu
#undef je32_to_cpu
#undef jemode_to_cpu
extern int target_endian;
#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); })
#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); })
#define cpu_to_je16(x) ((jint16_t){t16(x)})
#define cpu_to_je32(x) ((jint32_t){t32(x)})
#define cpu_to_jemode(x) ((jmode_t){t32(x)})
#define je16_to_cpu(x) (t16((x).v16))
#define je32_to_cpu(x) (t32((x).v32))
#define jemode_to_cpu(x) (t32((x).m))
#endif /* __JFFS2_USER_H__ */

163
include/smiLynxEM.h
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/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* smiLynxEM.h
* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
*
*
* modification history
* --------------------
* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
*/
#ifndef _SMI_LYNX_EM_H_
#define _SMI_LYNX_EM_H_
/*
* SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
*/
#define VIDEO_MEM_SIZE 0x400000
/*
* Supported video modes for SMI Lynx E/EM/EM+
*/
#define VIDEO_MODES 7
#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */
/* VGA2:60/120Hz (pitch=1600) */
/* SMI810:VGA1:75Hz (pitch=1600) */
/* VGA2:75Hz (pitch=1600) */
#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */
#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */
#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */
#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */
#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */
#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */
/*
* ISA mapped regs
*/
#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
/*
* Video processor control
*/
typedef struct {
unsigned int control;
unsigned int colorKey;
unsigned int colorKeyMask;
unsigned int start;
unsigned short offset;
unsigned short width;
unsigned int fifoPrio;
unsigned int fifoERL;
unsigned int YUVtoRGB;
} SmiVideoProc;
/*
* Video window control
*/
typedef struct {
unsigned short top;
unsigned short left;
unsigned short bottom;
unsigned short right;
unsigned int srcStart;
unsigned short width;
unsigned short offset;
unsigned char hStretch;
unsigned char vStretch;
} SmiVideoWin;
/*
* Capture port control
*/
typedef struct {
unsigned int control;
unsigned short topClip;
unsigned short leftClip;
unsigned short srcHeight;
unsigned short srcWidth;
unsigned int srcBufStart1;
unsigned int srcBufStart2;
unsigned short srcOffset;
unsigned short fifoControl;
} SmiCapturePort;
/******************************************************************************/
/* Export Graphic Driver Control */
/******************************************************************************/
typedef struct {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
unsigned int vprBase;
unsigned int cprBase;
unsigned int frameAdrs;
unsigned int memSize;
unsigned int mode;
unsigned int gdfIndex;
unsigned int gdfBytesPP;
unsigned int fg;
unsigned int bg;
unsigned int plnSizeX;
unsigned int plnSizeY;
unsigned int winSizeX;
unsigned int winSizeY;
char modeIdent[80];
} GraphicDevice;
extern GraphicDevice smi;
/******************************************************************************/
/* Export Graphic Functions */
/******************************************************************************/
void *video_hw_init (void); /* returns GraphicDevice struct or NULL */
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
);
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
);
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
#endif /*_SMI_LYNX_EM_H_ */