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fsl-ddr: Fix the chip-select interleaving issue

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commit 1542fbdeec
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dave Liu 2009-11-12 07:26:37 +08:00 committed by Kumar Gala
parent 4f127980e0
commit 3ad95deb30
1 changed files with 3 additions and 4 deletions
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7
cpu/mpc8xxx/ddr/options.c
View file

@ -22,9 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
unsigned int ctrl_num)
{
unsigned int i;
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
const char *p;
#endif
/* Chip select options. */
@ -242,8 +240,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
simple_strtoul(p, NULL, 0);
}
}
#endif
if( (p = getenv("ba_intlv_ctl")) != NULL) {
if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
if (strcmp(p, "cs0_cs1") == 0)
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
else if (strcmp(p, "cs2_cs3") == 0)
@ -283,7 +283,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
break;
}
}
#endif
fsl_ddr_board_options(popts, pdimm, ctrl_num);