ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.0

Synchronize R-Car Gen2 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-03-04 22:50:54 +01:00 committed by Marek Vasut
parent 8719ca8113
commit 3abd800eb9
11 changed files with 66 additions and 20 deletions

View file

@ -489,8 +489,6 @@
}; };
&lvds1 { &lvds1 {
status = "okay";
ports { ports {
port@1 { port@1 {
lvds_connector: endpoint { lvds_connector: endpoint {

View file

@ -94,9 +94,8 @@
status = "okay"; status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&osc1_clk>; <&osc1_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0"; clock-names = "du.0", "du.1", "du.2", "dclkin.0";
ports { ports {
port@0 { port@0 {
@ -104,11 +103,21 @@
remote-endpoint = <&adv7511_in>; remote-endpoint = <&adv7511_in>;
}; };
}; };
};
};
&lvds0 {
ports {
port@1 { port@1 {
lvds_connector0: endpoint { lvds_connector0: endpoint {
}; };
}; };
port@2 { };
};
&lvds1 {
ports {
port@1 {
lvds_connector1: endpoint { lvds_connector1: endpoint {
}; };
}; };
@ -318,6 +327,10 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller; interrupt-controller;
onkey {
compatible = "dlg,da9063-onkey";
};
rtc { rtc {
compatible = "dlg,da9063-rtc"; compatible = "dlg,da9063-rtc";
}; };

View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7790 SoC * Device Tree Source for the R-Car H2 (R8A77900) SoC
* *
* Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2013-2014 Renesas Solutions Corp.
@ -1559,7 +1559,7 @@
sata0: sata@ee300000 { sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7790", compatible = "renesas,sata-r8a7790",
"renesas,rcar-gen2-sata"; "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>; reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>; clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@ -1570,7 +1570,7 @@
sata1: sata@ee500000 { sata1: sata@ee500000 {
compatible = "renesas,sata-r8a7790", compatible = "renesas,sata-r8a7790",
"renesas,rcar-gen2-sata"; "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>; reg = <0 0xee500000 0 0x200000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 814>; clocks = <&cpg CPG_MOD 814>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;

View file

@ -479,8 +479,6 @@
}; };
&lvds0 { &lvds0 {
status = "okay";
ports { ports {
port@1 { port@1 {
lvds_connector: endpoint { lvds_connector: endpoint {

View file

@ -482,8 +482,6 @@
}; };
&lvds0 { &lvds0 {
status = "okay";
ports { ports {
port@1 { port@1 {
lvds_connector: endpoint { lvds_connector: endpoint {

View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7791 SoC * Device Tree Source for the R-Car M2-W (R8A77910) SoC
* *
* Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2015 Renesas Electronics Corporation
* Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2013-2014 Renesas Solutions Corp.
@ -1543,7 +1543,7 @@
sata0: sata@ee300000 { sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7791", compatible = "renesas,sata-r8a7791",
"renesas,rcar-gen2-sata"; "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>; reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>; clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@ -1554,7 +1554,7 @@
sata1: sata@ee500000 { sata1: sata@ee500000 {
compatible = "renesas,sata-r8a7791", compatible = "renesas,sata-r8a7791",
"renesas,rcar-gen2-sata"; "renesas,rcar-gen2-sata";
reg = <0 0xee500000 0 0x2000>; reg = <0 0xee500000 0 0x200000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 814>; clocks = <&cpg CPG_MOD 814>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;

View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7792 SoC * Device Tree Source for the R-Car V2H (R8A77920) SoC
* *
* Copyright (C) 2016 Cogent Embedded Inc. * Copyright (C) 2016 Cogent Embedded Inc.
*/ */
@ -829,7 +829,6 @@
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7792"; compatible = "renesas,du-r8a7792";
reg = <0 0xfeb00000 0 0x40000>; reg = <0 0xfeb00000 0 0x40000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, clocks = <&cpg CPG_MOD 724>,

View file

@ -596,6 +596,10 @@
status = "okay"; status = "okay";
}; };
&cpu0 {
cpu0-supply = <&vdd_dvfs>;
};
&rwdt { &rwdt {
timeout-sec = <60>; timeout-sec = <60>;
status = "okay"; status = "okay";
@ -725,6 +729,18 @@
compatible = "dlg,da9063-watchdog"; compatible = "dlg,da9063-watchdog";
}; };
}; };
vdd_dvfs: regulator@68 {
compatible = "dlg,da9210";
reg = <0x68>;
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
}; };
&i2c4 { &i2c4 {

View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7793 SoC * Device Tree Source for the R-Car M2-N (R8A77930) SoC
* *
* Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2014-2015 Renesas Electronics Corporation
*/ */

View file

@ -405,6 +405,31 @@
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
&i2c7 {
status = "okay";
clock-frequency = <100000>;
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
interrupt-parent = <&gpio3>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
onkey {
compatible = "dlg,da9063-onkey";
};
rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
};
};
&mmcif0 { &mmcif0 {
pinctrl-0 = <&mmcif0_pins>; pinctrl-0 = <&mmcif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";

View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7794 SoC * Device Tree Source for the R-Car E2 (R8A77940) SoC
* *
* Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2014 Ulrich Hecht * Copyright (C) 2014 Ulrich Hecht
@ -1349,7 +1349,6 @@
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7794"; compatible = "renesas,du-r8a7794";
reg = <0 0xfeb00000 0 0x40000>; reg = <0 0xfeb00000 0 0x40000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;