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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
board: gdsys: Make gdsys osd hardware detection more robust
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This commit is contained in:
parent
5568fb4402
commit
3a990bfaea
5 changed files with 81 additions and 62 deletions
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@ -15,7 +15,6 @@
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#include "../common/dp501.h"
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#include "../common/osd.h"
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#include "../common/mclink.h"
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@ -99,8 +98,6 @@ enum {
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unsigned int mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
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static int setup_88e1518(const char *bus, unsigned char addr);
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
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@ -374,20 +371,16 @@ int last_stage_init(void)
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u16 fpga_features;
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int feature_carrier_speed = fpga_features & (1<<4);
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bool ch0_rgmii2_present = false;
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int old_bus = i2c_get_bus_num();
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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/* Turn on Parade DP501 */
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pca9698_direction_output(0x20, 9, 1);
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udelay(500000);
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if (!legacy) {
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/* Turn on Parade DP501 */
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pca9698_direction_output(0x20, 9, 1);
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udelay(500000);
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i2c_set_bus_num(dp501_i2c[0]);
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dp501_powerup(0x08);
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i2c_set_bus_num(old_bus);
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if (!legacy)
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ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
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}
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print_fpga_info(0, ch0_rgmii2_present);
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osd_probe(0);
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@ -9,6 +9,7 @@
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#include <i2c.h>
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#include <malloc.h>
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#include "dp501.h"
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#include <gdsys_fpga.h>
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#define CH7301_I2C_ADDR 0x75
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@ -24,6 +25,8 @@
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#define SIL1178_MASTER_I2C_ADDRESS 0x38
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#define SIL1178_SLAVE_I2C_ADDRESS 0x39
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#define DP501_I2C_ADDR 0x08
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#define PIXCLK_640_480_60 25180000
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enum {
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@ -54,18 +57,23 @@ u16 *buf;
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unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
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#ifdef CONFIG_SYS_CH7301
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int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
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#endif
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#ifdef CONFIG_SYS_SIL1178
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#ifdef CONFIG_SYS_CH7301_I2C
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int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
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#endif
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#ifdef CONFIG_SYS_SIL1178_I2C
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int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
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#endif
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#ifdef CONFIG_SYS_DP501_I2C
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int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
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#endif
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#ifdef CONFIG_SYS_MPC92469AC
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static void mpc92469ac_calc_parameters(unsigned int fout,
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unsigned int *post_div, unsigned int *feedback_div)
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@ -118,7 +126,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
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}
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
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{
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@ -283,6 +291,8 @@ int osd_probe(unsigned screen)
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u16 features;
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u8 value;
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int old_bus = i2c_get_bus_num();
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bool pixclock_present = false;
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bool output_driver_present = false;
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FPGA_GET_REG(0, osd.version, &version);
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FPGA_GET_REG(0, osd.features, &features);
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@ -297,51 +307,76 @@ int osd_probe(unsigned screen)
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printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
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screen, version/100, version%100, base_width, base_height);
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#ifdef CONFIG_SYS_CH7301
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i2c_set_bus_num(ch7301_i2c[screen]);
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value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
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if (value != 0x17) {
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printf(" Probing CH7301 failed, DID %02x\n", value);
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i2c_set_bus_num(old_bus);
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return -1;
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}
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
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#endif
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/* setup pixclock */
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#ifdef CONFIG_SYS_MPC92469AC
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pixclock_present = true;
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mpc92469ac_set(screen, PIXCLK_640_480_60);
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01
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#ifdef CONFIG_SYS_ICS8N3QV01_I2C
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i2c_set_bus_num(ics8n3qv01_i2c[screen]);
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ics8n3qv01_set(PIXCLK_640_480_60);
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if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
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ics8n3qv01_set(PIXCLK_640_480_60);
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pixclock_present = true;
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}
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#endif
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#ifdef CONFIG_SYS_SIL1178
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i2c_set_bus_num(sil1178_i2c[screen]);
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value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
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if (value != 0x06) {
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printf(" Probing SIL1178, DEV_IDL %02x\n", value);
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i2c_set_bus_num(old_bus);
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return -1;
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if (!pixclock_present)
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printf(" no pixelclock found\n");
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/* setup output driver */
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#ifdef CONFIG_SYS_CH7301_I2C
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i2c_set_bus_num(ch7301_i2c[screen]);
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if (!i2c_probe(CH7301_I2C_ADDR)) {
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value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
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if (value == 0x17) {
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
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output_driver_present = true;
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}
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}
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/* magic initialization sequence adapted from datasheet */
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i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
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#endif
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#ifdef CONFIG_SYS_SIL1178_I2C
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i2c_set_bus_num(sil1178_i2c[screen]);
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if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
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value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
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if (value == 0x06) {
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/*
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* magic initialization sequence,
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* adapted from datasheet
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*/
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i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
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i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
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output_driver_present = true;
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}
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}
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#endif
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#ifdef CONFIG_SYS_DP501_I2C
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i2c_set_bus_num(dp501_i2c[screen]);
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if (!i2c_probe(DP501_I2C_ADDR)) {
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dp501_powerup(DP501_I2C_ADDR);
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output_driver_present = true;
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}
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#endif
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if (!output_driver_present)
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printf(" no output driver found\n");
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FPGA_SET_REG(screen, osd.control, 0x0049);
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FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
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@ -34,7 +34,6 @@ static int wait_for_int(bool read)
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udelay(10);
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if (ctr++ > 5000) {
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printf("I2C timeout\n");
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return 1;
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}
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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@ -121,9 +121,7 @@
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{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
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#define CONFIG_DTT_TACH_LIMIT 0xa10
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#define CONFIG_SYS_ICS8N3QV01
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#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
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#define CONFIG_SYS_SIL1178
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#define CONFIG_SYS_SIL1178_I2C {0, 1}
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/* EBC peripherals */
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} while (0)
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#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
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/*
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* OSD hardware
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*/
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#define CONFIG_SYS_MPC92469AC
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/*
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* FLASH organization
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*/
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/*
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* OSD Setup
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*/
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#define CONFIG_SYS_ICS8N3QV01
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#define CONFIG_SYS_MPC92469AC
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#define CONFIG_SYS_OSD_SCREENS 1
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#define CONFIG_SYS_DP501_DIFFERENTIAL
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