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mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers

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HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
FSL bootlets code.

mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".

HW_DRAM_CTL8 is setup as the last element.

So skip the initialization of these DRAM_CTL registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2013-05-03 04:37:12 +00:00 committed by Stefano Babic
parent b0d4bf9f0c
commit 39a538d992
1 changed files with 15 additions and 2 deletions
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17
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{ {
} }
#ifdef CONFIG_MX28
static void initialize_dram_values(void) static void initialize_dram_values(void)
{ {
int i; int i;
@ -118,15 +119,27 @@ static void initialize_dram_values(void)
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#else
static void initialize_dram_values(void)
{
int i;
mxs_adjust_memory_params(dram_vals);
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#ifdef CONFIG_MX23
/* /*
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
* element to be set * element to be set
*/ */
writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
#endif
} }
#endif
static void mxs_mem_init_clock(void) static void mxs_mem_init_clock(void)
{ {