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mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers
HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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1 changed files with 15 additions and 2 deletions
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@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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{
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}
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}
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#ifdef CONFIG_MX28
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static void initialize_dram_values(void)
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static void initialize_dram_values(void)
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{
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{
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int i;
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int i;
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@ -118,15 +119,27 @@ static void initialize_dram_values(void)
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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}
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#else
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static void initialize_dram_values(void)
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{
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int i;
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mxs_adjust_memory_params(dram_vals);
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for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
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if (i == 8 || i == 27 || i == 28 || i == 35)
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continue;
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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}
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#ifdef CONFIG_MX23
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/*
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/*
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* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
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* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
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* element to be set
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* element to be set
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*/
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*/
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writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
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writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
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#endif
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}
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}
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#endif
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static void mxs_mem_init_clock(void)
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static void mxs_mem_init_clock(void)
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{
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{
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